hdl: make ClockSignal and ResetSignal usable on LHS.

Fixes #8.

nmigen/test/test_hdl_dsl.py

@@ -95,6 +95,24 @@ class DSLTestCase(FHDLTestCase):
                 msg="'Module' object has no attribute 'nonexistentattr'"):
             m.nonexistentattr
 
+    def test_clock_signal(self):
+        m = Module()
+        m.d.comb += ClockSignal("pix").eq(ClockSignal())
+        self.assertRepr(m._statements, """
+        (
+            (eq (clk pix) (clk sync))
+        )
+        """)
+
+    def test_reset_signal(self):
+        m = Module()
+        m.d.comb += ResetSignal("pix").eq(1)
+        self.assertRepr(m._statements, """
+        (
+            (eq (rst pix) (const 1'd1))
+        )
+        """)
+
     def test_If(self):
         m = Module()
         with m.If(self.s1):

nmigen/test/test_hdl_xfrm.py

@@ -135,6 +135,18 @@ class DomainLowererTestCase(FHDLTestCase):
         )
         """)
 
+    def test_lower_drivers(self):
+        pix = ClockDomain()
+        f = Fragment()
+        f.add_driver(ClockSignal("pix"), None)
+        f.add_driver(ResetSignal("pix"), "sync")
+
+        f = DomainLowerer({"pix": pix})(f)
+        self.assertEqual(f.drivers, {
+            None: SignalSet((pix.clk,)),
+            "sync": SignalSet((pix.rst,))
+        })
+
     def test_lower_wrong_domain(self):
         sync = ClockDomain()
         f = Fragment()