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hdl._ir, lib, vendor: add RequirePosedge, use it whenever required.

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Wanda 2024-04-28 20:04:16 +02:00 • committed by Catherine
parent d3c312cf96
commit 028d5d8073
9 changed files with 110 additions and 2 deletions
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25
tests/test_hdl_ir.py
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@ -3598,3 +3598,28 @@ class DomainLookupTestCase(FHDLTestCase):
self.assertIs(design.lookup_domain("sync", xm5), m1_c)
self.assertIs(design.lookup_domain("d", xm4), m4_d)
self.assertIs(design.lookup_domain("d", xm5), m5_d)
class RequirePosedgeTestCase(FHDLTestCase):
def test_require_ok(self):
m = Module()
m.domains.sync = ClockDomain()
m.submodules += RequirePosedge("sync")
Fragment.get(m, None).prepare()
def test_require_fail(self):
m = Module()
m.domains.sync = ClockDomain(clk_edge="neg")
m.submodules += RequirePosedge("sync")
with self.assertRaisesRegex(DomainRequirementFailed,
r"^Domain sync has a negedge clock, but posedge clock is required by top.U\$0 at .*$"):
Fragment.get(m, None).prepare()
def test_require_renamed(self):
m = Module()
m.domains.sync = ClockDomain(clk_edge="pos")
m.domains.test = ClockDomain(clk_edge="neg")
m.submodules += DomainRenamer("test")(RequirePosedge("sync"))
with self.assertRaisesRegex(DomainRequirementFailed,
r"^Domain test has a negedge clock, but posedge clock is required by top.U\$0 at .*$"):
Fragment.get(m, None).prepare()