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lib.fifo.AsyncFFSynchronizer: check input and output signal width

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This commit is contained in:
Robin Ole Heinemann 2020-10-28 00:41:01 +01:00 • committed by whitequark
parent 765c15c709
commit 05decc43b2
2 changed files with 20 additions and 4 deletions
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8
tests/test_lib_cdc.py
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@ -69,6 +69,14 @@ class AsyncFFSynchronizerTestCase(FHDLTestCase):
r"^AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not 'xxx'$"):
AsyncFFSynchronizer(Signal(), Signal(), o_domain="sync", async_edge="xxx")
def test_width_wrong(self):
with self.assertRaisesRegex(ValueError,
r"^AsyncFFSynchronizer input width must be 1, not 2$"):
AsyncFFSynchronizer(Signal(2), Signal(), o_domain="sync")
with self.assertRaisesRegex(ValueError,
r"^AsyncFFSynchronizer output width must be 1, not 2$"):
AsyncFFSynchronizer(Signal(), Signal(2), o_domain="sync")
def test_pos_edge(self):
i = Signal()
o = Signal()