lib.fifo.AsyncFFSynchronizer: check input and output signal width
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@ -128,16 +128,24 @@ class AsyncFFSynchronizer(Elaboratable):
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def __init__(self, i, o, *, o_domain="sync", stages=2, async_edge="pos", max_input_delay=None):
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def __init__(self, i, o, *, o_domain="sync", stages=2, async_edge="pos", max_input_delay=None):
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_check_stages(stages)
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_check_stages(stages)
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if len(i) != 1:
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raise ValueError("AsyncFFSynchronizer input width must be 1, not {}"
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.format(len(i)))
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if len(o) != 1:
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raise ValueError("AsyncFFSynchronizer output width must be 1, not {}"
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.format(len(o)))
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if async_edge not in ("pos", "neg"):
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raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
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"not {!r}"
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.format(async_edge))
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self.i = i
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self.i = i
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self.o = o
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self.o = o
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self._o_domain = o_domain
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self._o_domain = o_domain
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self._stages = stages
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self._stages = stages
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if async_edge not in ("pos", "neg"):
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raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
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"not {!r}"
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.format(async_edge))
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self._edge = async_edge
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self._edge = async_edge
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self._max_input_delay = max_input_delay
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self._max_input_delay = max_input_delay
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@ -69,6 +69,14 @@ class AsyncFFSynchronizerTestCase(FHDLTestCase):
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r"^AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not 'xxx'$"):
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r"^AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not 'xxx'$"):
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AsyncFFSynchronizer(Signal(), Signal(), o_domain="sync", async_edge="xxx")
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AsyncFFSynchronizer(Signal(), Signal(), o_domain="sync", async_edge="xxx")
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def test_width_wrong(self):
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with self.assertRaisesRegex(ValueError,
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r"^AsyncFFSynchronizer input width must be 1, not 2$"):
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AsyncFFSynchronizer(Signal(2), Signal(), o_domain="sync")
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with self.assertRaisesRegex(ValueError,
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r"^AsyncFFSynchronizer output width must be 1, not 2$"):
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AsyncFFSynchronizer(Signal(), Signal(2), o_domain="sync")
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def test_pos_edge(self):
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def test_pos_edge(self):
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i = Signal()
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i = Signal()
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o = Signal()
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o = Signal()
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