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lib.fifo.AsyncFFSynchronizer: check input and output signal width

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This commit is contained in:
Robin Ole Heinemann 2020-10-28 00:41:01 +01:00 committed by whitequark
parent 765c15c709
commit 05decc43b2
2 changed files with 20 additions and 4 deletions
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16
nmigen/lib/cdc.py
View file

@ -128,16 +128,24 @@ class AsyncFFSynchronizer(Elaboratable):
def __init__(self, i, o, *, o_domain="sync", stages=2, async_edge="pos", max_input_delay=None):
_check_stages(stages)
if len(i) != 1:
raise ValueError("AsyncFFSynchronizer input width must be 1, not {}"
.format(len(i)))
if len(o) != 1:
raise ValueError("AsyncFFSynchronizer output width must be 1, not {}"
.format(len(o)))
if async_edge not in ("pos", "neg"):
raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
"not {!r}"
.format(async_edge))
self.i = i
self.o = o
self._o_domain = o_domain
self._stages = stages
if async_edge not in ("pos", "neg"):
raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
"not {!r}"
.format(async_edge))
self._edge = async_edge
self._max_input_delay = max_input_delay

8
tests/test_lib_cdc.py
View file

@ -69,6 +69,14 @@ class AsyncFFSynchronizerTestCase(FHDLTestCase):
r"^AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not 'xxx'$"):
AsyncFFSynchronizer(Signal(), Signal(), o_domain="sync", async_edge="xxx")
def test_width_wrong(self):
with self.assertRaisesRegex(ValueError,
r"^AsyncFFSynchronizer input width must be 1, not 2$"):
AsyncFFSynchronizer(Signal(2), Signal(), o_domain="sync")
with self.assertRaisesRegex(ValueError,
r"^AsyncFFSynchronizer output width must be 1, not 2$"):
AsyncFFSynchronizer(Signal(), Signal(2), o_domain="sync")
def test_pos_edge(self):
i = Signal()
o = Signal()