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back.pysim: check for a clock being added twice.

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This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.
This commit is contained in:
whitequark 2019-06-11 03:54:22 +00:00
parent d2d8c2b8bf
commit 066dd799e8
2 changed files with 12 additions and 0 deletions
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5
nmigen/back/pysim.py
View file

@ -366,6 +366,7 @@ class Simulator:
self._delta = 0.
self._epsilon = 1e-10
self._fastest_clock = self._epsilon
self._all_clocks = set() # {str/domain}
self._state = _State()
self._processes = set() # {process}
@ -426,6 +427,9 @@ class Simulator:
def add_clock(self, period, phase=None, domain="sync"):
if self._fastest_clock == self._epsilon or period < self._fastest_clock:
self._fastest_clock = period
if domain in self._all_clocks:
raise ValueError("Domain '{}' already has a clock driving it"
.format(domain))
half_period = period / 2
if phase is None:
@ -440,6 +444,7 @@ class Simulator:
yield clk.eq(0)
yield Delay(half_period)
self.add_process(clk_process)
self._all_clocks.add(domain)
def __enter__(self):
if self._vcd_file:

7
nmigen/test/test_sim.py
View file

@ -388,6 +388,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
"a generator function"):
sim.add_process(1)
def test_add_clock_wrong(self):
with self.assertSimulation(Module()) as sim:
sim.add_clock(1)
with self.assertRaises(ValueError,
msg="Domain 'sync' already has a clock driving it"):
sim.add_clock(1)
def test_eq_signal_unused_wrong(self):
self.setUp_lhs_rhs()
self.s = Signal()