back.pysim: check for a clock being added twice.

This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.

nmigen/test/test_sim.py

@@ -388,6 +388,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
                         "a generator function"):
                 sim.add_process(1)
 
+    def test_add_clock_wrong(self):
+        with self.assertSimulation(Module()) as sim:
+            sim.add_clock(1)
+            with self.assertRaises(ValueError,
+                    msg="Domain 'sync' already has a clock driving it"):
+                sim.add_clock(1)
+
     def test_eq_signal_unused_wrong(self):
         self.setUp_lhs_rhs()
         self.s = Signal()