hdl.mem: cast reset value for transparent read ports to integer.

2020-07-30 08:05:18 +01:00 · 2020-07-30 08:05:18 +01:00 · 07dc163105
parent 20f9ab9d7a
commit 07dc163105
1 changed files with 1 additions and 1 deletions
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@ -145,7 +145,7 @@ class ReadPort(Elaboratable):
            # value of the data output is forcibly set to the 0th initial value, if any--note that
            # many FPGAs do not guarantee this behavior!
            if len(self.memory.init) > 0:
-                self.data.reset = self.memory.init[0]
+                self.data.reset = operator.index(self.memory.init[0])
            latch_addr = Signal.like(self.addr)
            f.add_statements(
                latch_addr.eq(self.addr),