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hdl.mem: cast reset value for transparent read ports to integer.

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Adam Greig 2020-07-30 08:05:18 +01:00 committed by GitHub
parent 20f9ab9d7a
commit 07dc163105
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nmigen/hdl/mem.py
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@ -145,7 +145,7 @@ class ReadPort(Elaboratable):
# value of the data output is forcibly set to the 0th initial value, if any--note that # value of the data output is forcibly set to the 0th initial value, if any--note that
# many FPGAs do not guarantee this behavior! # many FPGAs do not guarantee this behavior!
if len(self.memory.init) > 0: if len(self.memory.init) > 0:
self.data.reset = self.memory.init[0] self.data.reset = operator.index(self.memory.init[0])
latch_addr = Signal.like(self.addr) latch_addr = Signal.like(self.addr)
f.add_statements( f.add_statements(
latch_addr.eq(self.addr), latch_addr.eq(self.addr),