test.sim: add tests for sync functionality and errors.
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whitequark
parent
7fa82a70be
commit
07e9cfa939
3 changed files with 189 additions and 3 deletions
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@ -1,6 +1,10 @@
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from contextlib import contextmanager
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from .tools import *
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from ..tools import flatten, union
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from ..hdl.ast import *
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from ..hdl.cd import *
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from ..hdl.dsl import *
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from ..hdl.ir import *
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from ..back.pysim import *
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@ -198,3 +202,185 @@ class SimulatorUnitTestCase(FHDLTestCase):
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stmt = lambda y, a: y.eq(array[a].p + array[a].n)
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for i in range(10):
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self.assertStatement(stmt, [C(i)], C(0))
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class SimulatorIntegrationTestCase(FHDLTestCase):
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@contextmanager
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def assertSimulation(self, module, deadline=None):
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with Simulator(module.lower(platform=None)) as sim:
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yield sim
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if deadline is None:
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sim.run()
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else:
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sim.run_until(deadline)
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def setUp_counter(self):
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self.count = Signal(3, reset=4)
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self.sync = ClockDomain()
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self.m = Module()
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self.m.d.sync += self.count.eq(self.count + 1)
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self.m.domains += self.sync
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def test_counter_process(self):
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self.setUp_counter()
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with self.assertSimulation(self.m) as sim:
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def process():
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self.assertEqual((yield self.count), 4)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 4)
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yield self.sync.clk.eq(1)
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self.assertEqual((yield self.count), 5)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 5)
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yield self.sync.clk.eq(0)
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self.assertEqual((yield self.count), 5)
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for _ in range(3):
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yield Delay(1e-6)
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yield self.sync.clk.eq(1)
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yield Delay(1e-6)
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yield self.sync.clk.eq(0)
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self.assertEqual((yield self.count), 0)
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sim.add_process(process)
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def test_counter_clock_and_sync_process(self):
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self.setUp_counter()
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with self.assertSimulation(self.m) as sim:
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sim.add_clock(1e-6, domain="sync")
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def process():
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self.assertEqual((yield self.count), 4)
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self.assertEqual((yield self.sync.clk), 0)
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yield
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self.assertEqual((yield self.count), 5)
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self.assertEqual((yield self.sync.clk), 1)
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for _ in range(3):
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yield
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self.assertEqual((yield self.count), 0)
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sim.add_sync_process(process)
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def setUp_alu(self):
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self.a = Signal(8)
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self.b = Signal(8)
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self.o = Signal(8)
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self.x = Signal(8)
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self.s = Signal(2)
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self.sync = ClockDomain(reset_less=True)
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self.m = Module()
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self.m.d.comb += self.x.eq(self.a ^ self.b)
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with self.m.Switch(self.s):
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with self.m.Case(0):
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self.m.d.sync += self.o.eq(self.a + self.b)
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with self.m.Case(1):
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self.m.d.sync += self.o.eq(self.a - self.b)
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with self.m.Case():
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self.m.d.sync += self.o.eq(0)
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self.m.domains += self.sync
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def test_alu(self):
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self.setUp_alu()
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with self.assertSimulation(self.m) as sim:
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sim.add_clock(1e-6)
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def process():
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yield self.a.eq(5)
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yield self.b.eq(1)
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yield
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self.assertEqual((yield self.x), 4)
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self.assertEqual((yield self.o), 6)
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yield self.s.eq(1)
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yield
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self.assertEqual((yield self.o), 4)
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yield self.s.eq(2)
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yield
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self.assertEqual((yield self.o), 0)
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sim.add_sync_process(process)
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def setUp_multiclock(self):
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self.sys = ClockDomain()
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self.pix = ClockDomain()
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self.m = Module()
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self.m.domains += self.sys, self.pix
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def test_multiclock(self):
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self.setUp_multiclock()
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with self.assertSimulation(self.m) as sim:
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sim.add_clock(1e-6, domain="sys")
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sim.add_clock(0.3e-6, domain="pix")
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def sys_process():
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yield Passive()
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yield
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yield
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self.fail()
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def pix_process():
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yield
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yield
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yield
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sim.add_sync_process(sys_process, domain="sys")
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sim.add_sync_process(pix_process, domain="pix")
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def setUp_lhs_rhs(self):
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self.i = Signal(8)
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self.o = Signal(8)
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self.m = Module()
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self.m.d.comb += self.o.eq(self.i)
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def test_complex_lhs_rhs(self):
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self.setUp_lhs_rhs()
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with self.assertSimulation(self.m) as sim:
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def process():
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yield self.i.eq(0b10101010)
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yield self.i[:4].eq(-1)
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yield Delay()
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self.assertEqual((yield self.i[:4]), 0b1111)
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self.assertEqual((yield self.i), 0b10101111)
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sim.add_process(process)
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def test_run_until(self):
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with self.assertSimulation(Module(), deadline=100e-6) as sim:
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sim.add_clock(1e-6)
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def process():
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for _ in range(100):
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yield
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self.fail()
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def test_add_process_wrong(self):
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with self.assertSimulation(Module()) as sim:
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with self.assertRaises(TypeError,
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msg="Cannot add a process '1' because it is not a generator or "
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"a generator function"):
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sim.add_process(1)
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def test_eq_signal_unused_wrong(self):
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self.setUp_lhs_rhs()
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self.s = Signal()
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with self.assertSimulation(self.m) as sim:
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def process():
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with self.assertRaisesRegex(ValueError,
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regex=r"Process '.+?' sent a request to set signal '\(sig s\)', "
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r"which is not a part of simulation"):
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yield self.s.eq(0)
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yield Delay()
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sim.add_process(process)
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def test_eq_signal_comb_wrong(self):
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self.setUp_lhs_rhs()
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with self.assertSimulation(self.m) as sim:
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def process():
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with self.assertRaisesRegex(ValueError,
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regex=r"Process '.+?' sent a request to set signal '\(sig o\)', "
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r"which is a part of combinatorial assignment in simulation"):
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yield self.o.eq(0)
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yield Delay()
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sim.add_process(process)
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def test_command_wrong(self):
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with self.assertSimulation(Module()) as sim:
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def process():
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with self.assertRaisesRegex(TypeError,
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regex=r"Received unsupported command '1' from process '.+?'"):
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yield 1
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yield Delay()
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sim.add_process(process)
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