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lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.

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This is for consistency with other synchronizers.

Fixes #467.
This commit is contained in:
whitequark 2020-08-26 03:19:13 +00:00
parent 630c0fd99a
commit 0802f943ba
7 changed files with 13 additions and 13 deletions
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4
nmigen/vendor/intel.py
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@ -402,7 +402,7 @@ class IntelPlatform(TemplatedPlatform):
if async_ff_sync._edge == "pos":
m.submodules += Instance("altera_std_synchronizer",
p_depth=async_ff_sync._stages,
i_clk=ClockSignal(async_ff_sync._domain),
i_clk=ClockSignal(async_ff_sync._o_domain),
i_reset_n=~async_ff_sync.i,
i_din=Const(1),
o_dout=sync_output,
@ -410,7 +410,7 @@ class IntelPlatform(TemplatedPlatform):
else:
m.submodules += Instance("altera_std_synchronizer",
p_depth=async_ff_sync._stages,
i_clk=ClockSignal(async_ff_sync._domain),
i_clk=ClockSignal(async_ff_sync._o_domain),
i_reset_n=async_ff_sync.i,
i_din=Const(1),
o_dout=sync_output,

2
nmigen/vendor/xilinx_7series.py
View file

@ -613,7 +613,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
m.d.comb += [
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
async_ff_sync.o.eq(flops[-1])
]

2
nmigen/vendor/xilinx_spartan_3_6.py
View file

@ -456,7 +456,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
m.d.comb += [
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
async_ff_sync.o.eq(flops[-1])
]

2
nmigen/vendor/xilinx_ultrascale.py
View file

@ -429,7 +429,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
m.d.comb += [
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
async_ff_sync.o.eq(flops[-1])
]