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lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.

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This is for consistency with other synchronizers.

Fixes #467.
This commit is contained in:
whitequark 2020-08-26 03:19:13 +00:00
parent 630c0fd99a
commit 0802f943ba
7 changed files with 13 additions and 13 deletions
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10
nmigen/lib/cdc.py
View file

@ -109,7 +109,7 @@ class AsyncFFSynchronizer(Elaboratable):
Asynchronous input signal, to be synchronized.
o : Signal(1), out
Synchronously released output signal.
domain : str
o_domain : str
Name of clock domain to synchronize to.
stages : int, >=2
Number of synchronization stages between input and output. The lowest safe number is 2,
@ -125,13 +125,13 @@ class AsyncFFSynchronizer(Elaboratable):
Define the ``get_async_ff_sync`` platform method to override the implementation of
:class:`AsyncFFSynchronizer`, e.g. to instantiate library cells directly.
"""
def __init__(self, i, o, *, domain="sync", stages=2, async_edge="pos", max_input_delay=None):
def __init__(self, i, o, *, o_domain="sync", stages=2, async_edge="pos", max_input_delay=None):
_check_stages(stages)
self.i = i
self.o = o
self._domain = domain
self._o_domain = o_domain
self._stages = stages
if async_edge not in ("pos", "neg"):
@ -164,7 +164,7 @@ class AsyncFFSynchronizer(Elaboratable):
m.d.comb += ResetSignal("async_ff").eq(~self.i)
m.d.comb += [
ClockSignal("async_ff").eq(ClockSignal(self._domain)),
ClockSignal("async_ff").eq(ClockSignal(self._o_domain)),
self.o.eq(flops[-1])
]
@ -212,7 +212,7 @@ class ResetSynchronizer(Elaboratable):
self._max_input_delay = max_input_delay
def elaborate(self, platform):
return AsyncFFSynchronizer(self.arst, ResetSignal(self._domain), domain=self._domain,
return AsyncFFSynchronizer(self.arst, ResetSignal(self._domain), o_domain=self._domain,
stages=self._stages, max_input_delay=self._max_input_delay)

2
nmigen/lib/fifo.py
View file

@ -416,7 +416,7 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
# Async-set-sync-release synchronizer avoids CDC hazards
rst_cdc = m.submodules.rst_cdc = \
AsyncFFSynchronizer(w_rst, r_rst, domain=self._r_domain)
AsyncFFSynchronizer(w_rst, r_rst, o_domain=self._r_domain)
# Decode Gray code counter synchronized from write domain to overwrite binary
# counter in read domain.

2
nmigen/test/test_lib_cdc.py
View file

@ -66,7 +66,7 @@ class AsyncFFSynchronizerTestCase(FHDLTestCase):
def test_edge_wrong(self):
with self.assertRaisesRegex(ValueError,
r"^AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not 'xxx'$"):
AsyncFFSynchronizer(Signal(), Signal(), domain="sync", async_edge="xxx")
AsyncFFSynchronizer(Signal(), Signal(), o_domain="sync", async_edge="xxx")
def test_pos_edge(self):
i = Signal()

4
nmigen/vendor/intel.py
View file

@ -402,7 +402,7 @@ class IntelPlatform(TemplatedPlatform):
if async_ff_sync._edge == "pos":
m.submodules += Instance("altera_std_synchronizer",
p_depth=async_ff_sync._stages,
i_clk=ClockSignal(async_ff_sync._domain),
i_clk=ClockSignal(async_ff_sync._o_domain),
i_reset_n=~async_ff_sync.i,
i_din=Const(1),
o_dout=sync_output,
@ -410,7 +410,7 @@ class IntelPlatform(TemplatedPlatform):
else:
m.submodules += Instance("altera_std_synchronizer",
p_depth=async_ff_sync._stages,
i_clk=ClockSignal(async_ff_sync._domain),
i_clk=ClockSignal(async_ff_sync._o_domain),
i_reset_n=async_ff_sync.i,
i_din=Const(1),
o_dout=sync_output,

2
nmigen/vendor/xilinx_7series.py
View file

@ -613,7 +613,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
m.d.comb += [
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
async_ff_sync.o.eq(flops[-1])
]

2
nmigen/vendor/xilinx_spartan_3_6.py
View file

@ -456,7 +456,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
m.d.comb += [
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
async_ff_sync.o.eq(flops[-1])
]

2
nmigen/vendor/xilinx_ultrascale.py
View file

@ -429,7 +429,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
m.d.comb += [
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
async_ff_sync.o.eq(flops[-1])
]