hdl.ast: make Slice const-castable.

Fixes #1006.

tests/test_hdl_ast.py

@@ -799,6 +799,16 @@ class SliceTestCase(FHDLTestCase):
         s1 = Const(10)[2]
         self.assertEqual(repr(s1), "(slice (const 4'd10) 2:3)")
 
+    def test_const(self):
+        a = Const.cast(Const(0x1234, 16)[4:12])
+        self.assertEqual(a.value, 0x23)
+        self.assertEqual(a.width, 8)
+        self.assertEqual(a.signed, False)
+        a = Const.cast(Const(-4, signed(8))[1:6])
+        self.assertEqual(a.value, 0x1e)
+        self.assertEqual(a.width, 5)
+        self.assertEqual(a.signed, False)
+
 
 class BitSelectTestCase(FHDLTestCase):
     def setUp(self):
@@ -1197,6 +1207,12 @@ class SignalTestCase(FHDLTestCase):
         self.assertEqual(s2.shape(), signed(2))
         self.assertEqual(s2.decoder(SignedEnum.FOO), "FOO/-1")
 
+    def test_const_wrong(self):
+        s1 = Signal()
+        with self.assertRaisesRegex(TypeError,
+                r"^Value \(sig s1\) cannot be converted to an Amaranth constant$"):
+            Const.cast(s1)
+
 
 class ClockSignalTestCase(FHDLTestCase):
     def test_domain(self):