sim.pysim: use VCD aliases to reduce space and time overhead.
On Minerva SoC, this reduces VCD file size by about 35%, and reduces runtime overhead of writing VCDs by 10% or less.
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0a90aa1b17
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@ -111,23 +111,25 @@ class _VCDWaveformWriter(_WaveformWriter):
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var_name_suffix = var_name
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var_name_suffix = var_name
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else:
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else:
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var_name_suffix = "{}${}".format(var_name, suffix)
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var_name_suffix = "{}${}".format(var_name, suffix)
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if signal not in self.vcd_vars:
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vcd_var = self.vcd_writer.register_var(
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vcd_var = self.vcd_writer.register_var(
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scope=var_scope, name=var_name_suffix,
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scope=var_scope, name=var_name_suffix,
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var_type=var_type, size=var_size, init=var_init)
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var_type=var_type, size=var_size, init=var_init)
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self.vcd_vars[signal] = vcd_var
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else:
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self.vcd_writer.register_alias(
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scope=var_scope, name=var_name_suffix,
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var=self.vcd_vars[signal])
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break
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break
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except KeyError:
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except KeyError:
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suffix = (suffix or 0) + 1
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suffix = (suffix or 0) + 1
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if signal not in self.vcd_vars:
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self.vcd_vars[signal] = set()
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self.vcd_vars[signal].add(vcd_var)
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if signal not in self.gtkw_names:
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if signal not in self.gtkw_names:
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self.gtkw_names[signal] = (*var_scope, var_name_suffix)
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self.gtkw_names[signal] = (*var_scope, var_name_suffix)
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def update(self, timestamp, signal, value):
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def update(self, timestamp, signal, value):
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vcd_vars = self.vcd_vars.get(signal)
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vcd_var = self.vcd_vars.get(signal)
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if vcd_vars is None:
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if vcd_var is None:
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return
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return
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vcd_timestamp = self.timestamp_to_vcd(timestamp)
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vcd_timestamp = self.timestamp_to_vcd(timestamp)
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@ -135,7 +137,6 @@ class _VCDWaveformWriter(_WaveformWriter):
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var_value = self.decode_to_vcd(signal, value)
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var_value = self.decode_to_vcd(signal, value)
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else:
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else:
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var_value = value
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var_value = value
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for vcd_var in vcd_vars:
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self.vcd_writer.change(vcd_var, vcd_timestamp, var_value)
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self.vcd_writer.change(vcd_var, vcd_timestamp, var_value)
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def close(self, timestamp):
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def close(self, timestamp):
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2
setup.py
2
setup.py
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@ -40,7 +40,7 @@ setup(
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install_requires=[
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install_requires=[
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"importlib_metadata; python_version<'3.8'", # for __version__ and nmigen._yosys
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"importlib_metadata; python_version<'3.8'", # for __version__ and nmigen._yosys
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"importlib_resources; python_version<'3.9'", # for nmigen._yosys
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"importlib_resources; python_version<'3.9'", # for nmigen._yosys
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"pyvcd~=0.2.0", # for nmigen.pysim
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"pyvcd~=0.2.2", # for nmigen.pysim
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"Jinja2~=2.11", # for nmigen.build
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"Jinja2~=2.11", # for nmigen.build
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],
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],
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extras_require={
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extras_require={
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