compat.sim: match clock period.
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@ -18,7 +18,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name
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with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
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with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
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for domain, period in clocks.items():
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for domain, period in clocks.items():
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sim.add_clock(period, domain)
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sim.add_clock(period / 1e9, domain)
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for domain, process in generators.items():
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for domain, process in generators.items():
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sim.add_sync_process(process, domain)
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sim.add_sync_process(process, domain)
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sim.run()
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sim.run()
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