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fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.

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This commit is contained in:
whitequark 2018-12-12 12:38:24 +00:00
parent 00f0b950f6
commit 0fac1f8d0f
9 changed files with 92 additions and 96 deletions
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20
examples/alu.py
View file

@ -11,16 +11,16 @@ class ALU:
self.co = Signal()
def get_fragment(self, platform):
f = Module()
with f.If(self.sel == 0b00):
f.comb += self.o.eq(self.a | self.b)
with f.Elif(self.sel == 0b01):
f.comb += self.o.eq(self.a & self.b)
with f.Elif(self.sel == 0b10):
f.comb += self.o.eq(self.a ^ self.b)
with f.Else():
f.comb += Cat(self.o, self.co).eq(self.a - self.b)
return f.lower(platform)
m = Module()
with m.If(self.sel == 0b00):
m.d.comb += self.o.eq(self.a | self.b)
with m.Elif(self.sel == 0b01):
m.d.comb += self.o.eq(self.a & self.b)
with m.Elif(self.sel == 0b10):
m.d.comb += self.o.eq(self.a ^ self.b)
with m.Else():
m.d.comb += Cat(self.o, self.co).eq(self.a - self.b)
return m.lower(platform)
alu = ALU(width=16)

30
examples/alu_hier.py
View file

@ -9,9 +9,9 @@ class Adder:
self.o = Signal(width)
def get_fragment(self, platform):
f = Module()
f.comb += self.o.eq(self.a + self.b)
return f.lower(platform)
m = Module()
m.d.comb += self.o.eq(self.a + self.b)
return m.lower(platform)
class Subtractor:
@ -21,9 +21,9 @@ class Subtractor:
self.o = Signal(width)
def get_fragment(self, platform):
f = Module()
f.comb += self.o.eq(self.a - self.b)
return f.lower(platform)
m = Module()
m.d.comb += self.o.eq(self.a - self.b)
return m.lower(platform)
class ALU:
@ -37,20 +37,20 @@ class ALU:
self.sub = Subtractor(width)
def get_fragment(self, platform):
f = Module()
f.submodules.add = self.add
f.submodules.sub = self.sub
f.comb += [
m = Module()
m.submodules.add = self.add
m.submodules.sub = self.sub
m.d.comb += [
self.add.a.eq(self.a),
self.sub.a.eq(self.a),
self.add.b.eq(self.b),
self.sub.b.eq(self.b),
]
with f.If(self.op):
f.comb += self.o.eq(self.sub.o)
with f.Else():
f.comb += self.o.eq(self.add.o)
return f.lower(platform)
with m.If(self.op):
m.d.comb += self.o.eq(self.sub.o)
with m.Else():
m.d.comb += self.o.eq(self.add.o)
return m.lower(platform)
alu = ALU(width=16)

14
examples/arst.py
View file

@ -8,14 +8,14 @@ class ClockDivisor:
self.o = Signal()
def get_fragment(self, platform):
f = Module()
f.sync += self.v.eq(self.v + 1)
f.comb += self.o.eq(self.v[-1])
return f.lower(platform)
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m.lower(platform)
sys = ClockDomain(async_reset=True)
sync = ClockDomain(async_reset=True)
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys}))
# print(rtlil.convert(frag, ports=[sync.clk, sync.reset, ctr.o], clock_domains={"sync": sync}))
print(verilog.convert(frag, ports=[sync.clk, sync.reset, ctr.o], clock_domains={"sync": sync}))

14
examples/clkdiv.py
View file

@ -8,14 +8,14 @@ class ClockDivisor:
self.o = Signal()
def get_fragment(self, platform):
f = Module()
f.sync += self.v.eq(self.v + 1)
f.comb += self.o.eq(self.v[-1])
return f.lower(platform)
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m.lower(platform)
sys = ClockDomain()
sync = ClockDomain()
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sys.clk, ctr.o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[sys.clk, ctr.o], clock_domains={"sys": sys}))
# print(rtlil.convert(frag, ports=[sync.clk, ctr.o], clock_domains={"sync": sync}))
print(verilog.convert(frag, ports=[sync.clk, ctr.o], clock_domains={"sync": sync}))

14
examples/ctrl.py
View file

@ -9,14 +9,14 @@ class ClockDivisor:
self.ce = Signal()
def get_fragment(self, platform):
f = Module()
f.sync += self.v.eq(self.v + 1)
f.comb += self.o.eq(self.v[-1])
return CEInserter(self.ce)(f.lower())
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return CEInserter(self.ce)(m.lower(platform))
sys = ClockDomain()
sync = ClockDomain()
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sys.clk, ctr.o, ctr.ce], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[sys.clk, ctr.o, ctr.ce], clock_domains={"sys": sys}))
# print(rtlil.convert(frag, ports=[sync.clk, ctr.o, ctr.ce], clock_domains={"sync": sync}))
print(verilog.convert(frag, ports=[sync.clk, ctr.o, ctr.ce], clock_domains={"sync": sync}))

20
examples/pmux.py
View file

@ -11,16 +11,16 @@ class ParMux:
self.o = Signal(width)
def get_fragment(self, platform):
f = Module()
with f.Case(self.s, "--1"):
f.comb += self.o.eq(self.a)
with f.Case(self.s, "-1-"):
f.comb += self.o.eq(self.b)
with f.Case(self.s, "1--"):
f.comb += self.o.eq(self.c)
with f.Case(self.s):
f.comb += self.o.eq(0)
return f.lower(platform)
m = Module()
with m.Case(self.s, "--1"):
m.d.comb += self.o.eq(self.a)
with m.Case(self.s, "-1-"):
m.d.comb += self.o.eq(self.b)
with m.Case(self.s, "1--"):
m.d.comb += self.o.eq(self.c)
with m.Case(self.s):
m.d.comb += self.o.eq(0)
return m.lower(platform)
pmux = ParMux(width=16)