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fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.

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This commit is contained in:
whitequark 2018-12-12 12:38:24 +00:00
parent 00f0b950f6
commit 0fac1f8d0f
9 changed files with 92 additions and 96 deletions
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4
nmigen/back/rtlil.py
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@ -449,11 +449,13 @@ def convert_fragment(builder, fragment, name, clock_domains):
triggers = []
if cd_name is None:
triggers.append(("always",))
else:
elif cd_name in clock_domains:
cd = clock_domains[cd_name]
triggers.append(("posedge", xformer(cd.clk)))
if cd.async_reset:
triggers.append(("posedge", xformer(cd.reset)))
else:
raise ValueError("Clock domain {} not found in design".format(cd_name))
for trigger in triggers:
with process.sync(*trigger) as sync: