vendor: fix a few issues in commit 2f8669ca
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This commit is contained in:
parent
2f8669cad6
commit
12c79025f3
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@ -127,7 +127,8 @@ class AsyncFFSynchronizer(Elaboratable):
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self._stages = stages
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if async_edge not in ("pos", "neg"):
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raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not {!r}"
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raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
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"not {!r}"
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.format(async_edge))
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self._edge = async_edge
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2
nmigen/vendor/intel.py
vendored
2
nmigen/vendor/intel.py
vendored
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@ -403,7 +403,7 @@ class IntelPlatform(TemplatedPlatform):
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def get_async_ff_sync(self, async_ff_sync):
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m = Module()
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sync_output = Signal()
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if async_ff_sync.edge == "pos":
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if async_ff_sync._edge == "pos":
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m.submodules += Instance("altera_std_synchronizer",
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p_depth=async_ff_sync._stages,
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i_clk=ClockSignal(async_ff_sync._domain),
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2
nmigen/vendor/xilinx_7series.py
vendored
2
nmigen/vendor/xilinx_7series.py
vendored
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@ -420,7 +420,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
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for i, o in zip((0, *flops), flops):
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m.d.async_ff += o.eq(i)
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if self._edge == "pos":
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if async_ff_sync._edge == "pos":
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m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
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else:
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m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)
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2
nmigen/vendor/xilinx_spartan_3_6.py
vendored
2
nmigen/vendor/xilinx_spartan_3_6.py
vendored
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@ -451,7 +451,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
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for i, o in zip((0, *flops), flops):
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m.d.async_ff += o.eq(i)
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if self._edge == "pos":
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if async_ff_sync._edge == "pos":
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m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
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else:
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m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)
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2
nmigen/vendor/xilinx_ultrascale.py
vendored
2
nmigen/vendor/xilinx_ultrascale.py
vendored
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@ -416,7 +416,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
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for i, o in zip((0, *flops), flops):
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m.d.async_ff += o.eq(i)
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if self._edge == "pos":
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if async_ff_sync._edge == "pos":
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m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
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else:
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m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)
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