vendor: fix a few issues in commit 2f8669ca.

This commit is contained in:
whitequark 2020-03-12 20:28:41 +00:00
parent 2f8669cad6
commit 12c79025f3
5 changed files with 6 additions and 5 deletions

View file

@ -127,7 +127,8 @@ class AsyncFFSynchronizer(Elaboratable):
self._stages = stages
if async_edge not in ("pos", "neg"):
raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', not {!r}"
raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
"not {!r}"
.format(async_edge))
self._edge = async_edge

View file

@ -403,7 +403,7 @@ class IntelPlatform(TemplatedPlatform):
def get_async_ff_sync(self, async_ff_sync):
m = Module()
sync_output = Signal()
if async_ff_sync.edge == "pos":
if async_ff_sync._edge == "pos":
m.submodules += Instance("altera_std_synchronizer",
p_depth=async_ff_sync._stages,
i_clk=ClockSignal(async_ff_sync._domain),

View file

@ -420,7 +420,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
for i, o in zip((0, *flops), flops):
m.d.async_ff += o.eq(i)
if self._edge == "pos":
if async_ff_sync._edge == "pos":
m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
else:
m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)

View file

@ -451,7 +451,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
for i, o in zip((0, *flops), flops):
m.d.async_ff += o.eq(i)
if self._edge == "pos":
if async_ff_sync._edge == "pos":
m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
else:
m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)

View file

@ -416,7 +416,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
for i, o in zip((0, *flops), flops):
m.d.async_ff += o.eq(i)
if self._edge == "pos":
if async_ff_sync._edge == "pos":
m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
else:
m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)