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back.pysim: wake up processes before ever committing any values.

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Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
This commit is contained in:
whitequark 2019-01-21 16:00:25 +00:00
parent 52a9f818f1
commit 12e04e4ee5
2 changed files with 16 additions and 8 deletions
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14
nmigen/back/pysim.py
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@ -638,13 +638,6 @@ class Simulator:
while curr_domains:
domain = curr_domains.pop()
# Take the computed value (at the start of this delta cycle) of every sync signal
# in this domain and update the value for this delta cycle. This can trigger more
# synchronous logic, so record that.
for signal_slot in self._state.iter_next_dirty():
if self._domain_signals[domain][signal_slot]:
self._commit_signal(signal_slot, domains)
# Wake up any simulator processes that wait for a domain tick.
for process, wait_domain in list(self._wait_tick.items()):
if domain == wait_domain:
@ -658,6 +651,13 @@ class Simulator:
# values from the previous clock cycle on a tick, too.
self._run_process(process)
# Take the computed value (at the start of this delta cycle) of every sync signal
# in this domain and update the value for this delta cycle. This can trigger more
# synchronous logic, so record that.
for signal_slot in self._state.iter_next_dirty():
if self._domain_signals[domain][signal_slot]:
self._commit_signal(signal_slot, domains)
# Unless handling synchronous logic above has triggered more synchronous logic (which
# can happen e.g. if a domain is clocked off a clock divisor in fabric), we're done.
# Otherwise, do one more round of updates.