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back.pysim: wake up processes before ever committing any values.

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Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
This commit is contained in:
whitequark 2019-01-21 16:00:25 +00:00
parent 52a9f818f1
commit 12e04e4ee5
2 changed files with 16 additions and 8 deletions
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10
nmigen/test/test_sim.py
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@ -282,6 +282,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
self.assertEqual((yield self.count), 4)
self.assertEqual((yield self.sync.clk), 0)
yield
self.assertEqual((yield self.count), 4)
self.assertEqual((yield self.sync.clk), 1)
yield
self.assertEqual((yield self.count), 5)
self.assertEqual((yield self.sync.clk), 1)
for _ in range(3):
@ -317,12 +320,15 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
yield self.b.eq(1)
yield
self.assertEqual((yield self.x), 4)
yield
self.assertEqual((yield self.o), 6)
yield self.s.eq(1)
yield
yield
self.assertEqual((yield self.o), 4)
yield self.s.eq(2)
yield
yield
self.assertEqual((yield self.o), 0)
sim.add_sync_process(process)
@ -487,9 +493,11 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
yield self.wrport.en.eq(1)
yield self.rdport.en.eq(1)
yield
self.assertEqual((yield self.rdport.data), 0x00)
yield
self.assertEqual((yield self.rdport.data), 0xaa)
yield Delay(1e-6) # let comb propagate
self.assertEqual((yield self.rdport.data), 0xaa)
self.assertEqual((yield self.rdport.data), 0x33)
sim.add_clock(1e-6)
sim.add_sync_process(process)