whitequark
parent
1387e2f9df
commit
1334bd6a8b
1 changed files with 83 additions and 112 deletions
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@ -5,10 +5,10 @@ nMigen intends to provide as close to 100% compatibility to Migen as possible wi
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API change legend:
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- *id*: identical
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- *obs*: removed or irreversibly changed with compatibility stub provided
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- *obs →n*: removed or irreversibly changed with compatibility stub provided, use *n* instead
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- *brk*: removed or irreversibly changed with no replacement provided
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- *brk →n*: removed or irreversibly changed with no replacement provided, use *n* instead
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- *obs*: removed or incompatibly changed with compatibility stub provided
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- *obs →n*: removed or incompatibly changed with compatibility stub provided, use *n* instead
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- *brk*: removed or incompatibly changed with no replacement provided
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- *brk →n*: removed or incompatibly changed with no replacement provided, use *n* instead
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- *→n*: renamed to *n*
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- *⇒m*: merged into *m*
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- *a=→b=*: parameter *a* renamed to *b*
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@ -29,101 +29,83 @@ Compatibility summary
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---------------------
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- (−) `fhdl` → `.hdl`
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- (+) `bitcontainer` ⇒ `.tools`
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- (+) `log2_int` id
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- (+) `bits_for` id
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- (+) `value_bits_sign` → `Value.shape`
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- (−) `conv_output` ?
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- (+) `decorators` ⇒ `.hdl.xfrm`
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- (⊕) `bitcontainer` ⇒ `.tools`
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- (⊕) `log2_int` id
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- (⊕) `bits_for` id
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- (⊕) `value_bits_sign` → `Value.shape`
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- (⊕) `conv_output` **obs**
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- (⊕) `decorators` ⇒ `.hdl.xfrm`
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<br>Note: `transform_*` methods not considered part of public API.
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- (⊙) `ModuleTransformer` **brk**
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- (⊙) `ControlInserter` **brk**
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- (+) `CEInserter` → `EnableInserter`
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- (+) `ResetInserter` id
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- (+) `ClockDomainsRenamer` → `DomainRenamer`, `cd_remapping=`→`domain_map=`
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- (⊕) `CEInserter` → `EnableInserter`
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- (⊕) `ResetInserter` id
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- (⊕) `ClockDomainsRenamer` → `DomainRenamer`, `cd_remapping=`→`domain_map=`
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- (⊙) `edif` **brk**
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- (+) `module` **obs** → `.hdl.dsl`
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- (+) `FinalizeError` **obs**
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- (+) `Module` **obs** → `.hdl.dsl.Module`
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- (⊕) `module` **obs** → `.hdl.dsl`
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<br>Note: any class inheriting from `Module` in oMigen should inherit from `Elaboratable` in nMigen and use an nMigen `Module` in its `.elaborate()` method.
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- (⊕) `FinalizeError` **obs**
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- (⊕) `Module` **obs** → `.hdl.dsl.Module`
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- (⊙) `namer` **brk**
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- (−) `simplify` ?
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- (−) `FullMemoryWE` ?
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- (−) `MemoryToArray` ?
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- (−) `SplitMemory` ?
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- (⊙) `simplify` **brk**
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- (⊕) `specials` **obs**
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- (⊙) `Special` **brk**
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- (⊕) `Tristate` → `.lib.io.Tristate`, `target=`→`io=`
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- (⊕) `TSTriple` → `.lib.io.TSTriple`, `bits_sign=`→`shape=`
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- (⊕) `Tristate` **obs**
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- (⊕) `TSTriple` **obs** → `.lib.io.Pin`
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- (⊕) `Instance` → `.hdl.ir.Instance`
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- (⊕) `Memory` id
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<br>Note: nMigen memories should not be added as submodules.
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- (⊕) `.get_port` **obs** → `.read_port()` + `.write_port()`
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- (⊕) `_MemoryPort` **obs**
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<br>Note: nMigen separates read and write ports.
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- (⊕) `_MemoryPort` **obs** → `.hdl.mem.ReadPort` + `.hdl.mem.WritePort`
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- (⊕) `READ_FIRST`/`WRITE_FIRST` **obs**
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<br>Note: `READ_FIRST` corresponds to `mem.read_port(transparent=False)`, and `WRITE_FIRST` to `mem.read_port(transparent=True)`.
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- (⊙) `NO_CHANGE` **brk**
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<br>Note: in designs using `NO_CHANGE`, repalce it with an asynchronous read port and logic implementing required semantics explicitly.
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- (−) `structure` → `.hdl.ast`
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- (+) `DUID` id
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- (+) `_Value` → `Value`
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<br>Note: in designs using `NO_CHANGE`, replace it with logic implementing required semantics explicitly, or with a different mode.
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- (⊕) `structure` → `.hdl.ast`
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- (⊕) `DUID` id
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- (⊕) `_Value` → `Value`
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<br>Note: values no longer valid as keys in `dict` and `set`; use `ValueDict` and `ValueSet` instead.
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- (+) `wrap` → `Value.wrap`
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- (+) `_Operator` → `Operator`
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- (+) `Mux` id
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- (+) `_Slice` → `Slice`, `stop=`→`end=`, `.stop`→`.end`
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- (+) `_Part` → `Part`
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- (+) `Cat` id, `.l`→`.parts`
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- (+) `Replicate` → `Repl`, `v=`→`value=`, `n=`→`count=`, `.v`→`.value`, `.n`→`.count`
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- (+) `Constant` → `Const`, `bits_sign=`→`shape=`
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- (+) `Signal` id, `bits_sign=`→`shape=`, `attr=`→`attrs=`, `name_override=`∼, `related=`, `variable=`∼
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- (+) `ClockSignal` id, `cd=`→`domain=`
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- (+) `ResetSignal` id, `cd=`→`domain=`
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- (+) `_Statement` → `Statement`
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- (+) `_Assign` → `Assign`, `l=`→`lhs=`, `r=`→`rhs=`
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- (+) `_check_statement` **obs** → `Statement.wrap`
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- (+) `If` **obs** → `.hdl.dsl.Module.If`
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- (+) `Case` **obs** → `.hdl.dsl.Module.Switch`
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- (+) `_ArrayProxy` → `.hdl.ast.ArrayProxy`, `choices=`→`elems=`, `key=`→`index=`
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- (+) `Array` id
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- (+) `ClockDomain` → `.hdl.cd.ClockDomain`
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- (−) `_ClockDomainList` ?
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- (−) `SPECIAL_INPUT`/`SPECIAL_OUTPUT`/`SPECIAL_INOUT` ?
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- (⊕) `wrap` → `Value.cast`
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- (⊕) `_Operator` → `Operator`, `op=`→`operator=`, `.op`→`.operator`
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- (⊕) `Mux` id
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- (⊕) `_Slice` → `Slice` id
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- (⊕) `_Part` → `Part` id
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- (⊕) `Cat` id, `.l`→`.parts`
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- (⊕) `Replicate` → `Repl`, `v=`→`value=`, `n=`→`count=`, `.v`→`.value`, `.n`→`.count`
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- (⊕) `Constant` → `Const`, `bits_sign=`→`shape=`, `.nbits`→`.width`
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- (⊕) `Signal` id, `bits_sign=`→`shape=`, `attr=`→`attrs=`, `name_override=`∼, `related=`, `variable=`∼, `.nbits`→`.width`
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- (⊕) `ClockSignal` id, `cd=`→`domain=`, `.cd`→`.domain`
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- (⊕) `ResetSignal` id, `cd=`→`domain=`, `.cd`→`.domain`
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- (⊕) `_Statement` → `Statement`
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- (⊕) `_Assign` → `Assign`, `l=`→`lhs=`, `r=`→`rhs=`
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- (⊕) `_check_statement` **obs** → `Statement.cast`
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- (⊕) `If` **obs** → `.hdl.dsl.Module.If`
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- (⊕) `Case` **obs** → `.hdl.dsl.Module.Switch`
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- (⊕) `_ArrayProxy` → `.hdl.ast.ArrayProxy`, `choices=`→`elems=`, `key=`→`index=`
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- (⊕) `Array` id
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- (⊕) `ClockDomain` → `.hdl.cd.ClockDomain`
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- (⊙) `_ClockDomainList` **brk**
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- (⊙) `SPECIAL_INPUT`/`SPECIAL_OUTPUT`/`SPECIAL_INOUT` **brk**
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- (⊙) `_Fragment` **brk** → `.hdl.ir.Fragment`
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- (−) `tools` **brk**
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- (−) `list_signals` ?
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- (−) `list_targets` ?
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- (−) `list_inputs` ?
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- (−) `group_by_targets` ?
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- (⊙) `list_special_ios` **brk**
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- (⊙) `list_clock_domains_expr` **brk**
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- (−) `list_clock_domains` ?
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- (−) `is_variable` ?
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- (⊙) `generate_reset` **brk**
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- (⊙) `insert_reset` **brk**
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- (⊙) `tools` **brk**
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- (⊙) `insert_resets` **brk** → `.hdl.xfrm.ResetInserter`
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- (⊙) `lower_basics` **brk**
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- (⊙) `lower_complex_slices` **brk**
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- (⊙) `lower_complex_parts` **brk**
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- (⊙) `rename_clock_domain_expr` **brk**
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- (⊙) `rename_clock_domain` **brk** → `.hdl.xfrm.DomainRenamer`
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- (⊙) `call_special_classmethod` **brk**
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- (⊙) `lower_specials` **brk**
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- (−) `tracer` **brk**
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- (−) `get_var_name` ?
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- (−) `remove_underscore` ?
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- (−) `get_obj_var_name` ?
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- (−) `index_id` ?
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- (−) `trace_back` ?
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- (−) `verilog`
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- (−) `DummyAttrTranslate` ?
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- (−) `convert` **obs** → `.back.verilog.convert`
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- (⊙) `tracer` **brk**
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- (⊕) `get_var_name` → `.tracer.get_var_name`
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- (⊙) `remove_underscore` **brk**
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- (⊙) `get_obj_var_name` **brk**
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- (⊙) `index_id` **brk**
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- (⊙) `trace_back` **brk**
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- (⊙) `verilog`
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- (⊙) `DummyAttrTranslate` ?
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- (⊕) `convert` **obs** → `.back.verilog.convert`
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- (⊙) `visit` **brk** → `.hdl.xfrm`
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- (⊙) `NodeVisitor` **brk**
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- (⊙) `NodeTransformer` **brk** → `.hdl.xfrm.ValueTransformer`/`.hdl.xfrm.StatementTransformer`
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- (−) `genlib` → `.lib`
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- (−) `cdc` ?
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- (−) `MultiRegImpl` ?
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- (⊕) `MultiReg` id
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- (⊙) `MultiRegImpl` **brk**
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- (⊕) `MultiReg` → `.lib.cdc.FFSynchronizer`
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- (−) `PulseSynchronizer` ?
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- (−) `BusSynchronizer` ?
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- (⊕) `GrayCounter` **obs** → `.lib.coding.GrayEncoder`
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@ -139,24 +121,16 @@ Compatibility summary
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- (⊕) `PriorityDecoder` id
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- (−) `divider` ?
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- (−) `Divider` ?
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- (−) `fifo` ?
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- (⊕) `fifo` → `.lib.fifo`
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- (⊕) `_FIFOInterface` → `FIFOInterface`
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- (⊕) `SyncFIFO` id, `.fifo=`∼
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- (⊕) `SyncFIFO` id, `.replace=`∼
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- (⊕) `SyncFIFOBuffered` id, `.fifo=`∼
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- (−) `AsyncFIFO` ?
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- (−) `AsyncFIFOBuffered` ?
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- (+) `fsm` **obs**
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- (+) `AnonymousState` **obs**
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- (+) `NextState` **obs**
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- (+) `NextValue` **obs**
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- (+) `_LowerNext` **obs**
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- (+) `FSM` **obs**
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- (−) `io` ?
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- (−) `DifferentialInput` ?
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- (−) `DifferentialOutput` ?
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- (−) `CRG` ?
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- (−) `DDRInput` ?
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- (−) `DDROutput` ?
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- (⊕) `AsyncFIFO` ?
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- (⊕) `AsyncFIFOBuffered`, `.fifo=`∼
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- (⊕) `fsm` **obs**
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<br>Note: FSMs are a part of core nMigen DSL; however, not all functionality is provided. The compatibility shim is a complete port of Migen FSM module.
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- (⊙) `io` **brk**
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<br>Note: all functionality in this module is a part of nMigen platform system.
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- (−) `misc` ?
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- (−) `split` ?
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- (−) `displacer` ?
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@ -164,33 +138,30 @@ Compatibility summary
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- (−) `timeline` ?
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- (−) `WaitTimer` ?
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- (−) `BitSlip` ?
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- (−) `record` **obs** → `.hdl.rec.Record`
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- (−) `DIR_NONE` id
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- (−) `DIR_M_TO_S` → `DIR_FANOUT`
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- (−) `DIR_S_TO_M` → `DIR_FANIN`
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- (−) `set_layout_parameters` **brk**
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- (−) `layout_len` **brk**
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- (−) `layout_get` **brk**
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- (−) `layout_partial` **brk**
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- (−) `Record` id
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- (+) `resetsync` ?
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- (+) `AsyncResetSynchronizer` **obs** → `.lib.cdc.ResetSynchronizer`
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- (⊕) `record` **obs** → `.hdl.rec.Record`
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<br>Note: nMigen uses a `Layout` object to represent record layouts.
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- (⊕) `DIR_NONE` id
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- (⊕) `DIR_M_TO_S` → `DIR_FANOUT`
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- (⊕) `DIR_S_TO_M` → `DIR_FANIN`
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- (⊕) `Record` id
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- (⊙) `set_layout_parameters` **brk**
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- (⊙) `layout_len` **brk**
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- (⊙) `layout_get` **brk**
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- (⊙) `layout_partial` **brk**
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- (⊕) `resetsync` **obs**
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- (⊕) `AsyncResetSynchronizer` **obs** → `.lib.cdc.ResetSynchronizer`
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- (−) `roundrobin` ?
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- (−) `SP_WITHDRAW`/`SP_CE` ?
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- (−) `RoundRobin` ?
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- (−) `sort` ?
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- (−) `BitonicSort` ?
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- (-) `sim` **obs** → `.back.pysim`
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- (⊕) `sim` **obs** → `.back.pysim`
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<br>Note: only items directly under `nmigen.compat.sim`, not submodules, are provided.
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- (⊙) `core` **brk**
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- (⊙) `vcd` **brk** → `vcd`
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- (⊙) `Simulator` **brk**
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- (⊕) `run_simulation` **obs** → `.back.pysim.Simulator`
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- (⊕) `passive` **obs** → `.hdl.ast.Passive`
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- (−) `build` ?
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- (+) `util` **obs**
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- (+) `misc` ⇒ `.tools`
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- (+) `flat_iteration` → `.flatten`
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- (⊙) `xdir` **brk**
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- (⊙) `gcd_multiple` **brk**
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- (⊙) `treeviz` **brk**
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- (⊙) `build` **brk**
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<br>Note: the build system has been completely redesigned in nMigen.
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- (⊙) `util` **brk**
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