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vendor.xilinx_7series: byte swap generated bitstream

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The Zynq driver in the FPGA Manager framework on Linux expects bitstreams that
are byte swapped with respect to what the Vivado command
`write_bitstream -bin_file` produces. Thus, use the `write_cfgmem` command with
appropriate options to generate the bitstream (.bin file).

Fixes #519.
This commit is contained in:
Norbert Braun 2020-11-02 22:00:17 +01:00 committed by whitequark
parent b15f0562a6
commit 14a5c42a8b
1 changed files with 2 additions and 1 deletions
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3
nmigen/vendor/xilinx_7series.py
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@ -143,7 +143,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
report_power -file {{name}}_power.rpt
{{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
write_bitstream -force -bin_file {{name}}.bit
write_bitstream -force {{name}}.bit
write_cfgmem -force -format bin -interface smapx32 -disablebitswap -loadbit "up 0 {{name}}.bit" {{name}}.bin
{{get_override("script_after_bitstream")|default("# (script_after_bitstream placeholder)")}}
quit
""",