sim: use Value.cast on traces.

See kuznia-rdzeni/coreblocks#357.
2024-01-31 00:07:33 +01:00 · 2024-01-31 00:07:33 +01:00 · 1506f08b81
parent ea3d6c9557
commit 1506f08b81
1 changed files with 1 additions and 0 deletions
--- a/amaranth/sim/pysim.py
+++ b/amaranth/sim/pysim.py
@ -65,6 +65,7 @@ class _VCDWriter:
        trace_names = SignalDict()
        assigned_names = set()
        for trace in traces:
+            trace = Value.cast(trace)
            for trace_signal in trace._rhs_signals():
                if trace_signal not in signal_names:
                    if trace_signal.name not in assigned_names: