lib.data: fix typo.
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2 changed files with 2 additions and 2 deletions
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@ -635,7 +635,7 @@ class StructTestCase(FHDLTestCase):
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a: 1
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with self.assertRaisesRegex(TypeError,
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r"^Aggregate class 'Sd' must either inherits or specify a layout, not both$"):
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r"^Aggregate class 'Sd' must either inherit or specify a layout, not both$"):
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class Sd(Sb):
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b: 1
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