test_build_res: fix naming, squash warnings.
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Wanda
Catherine
parent
eebffc15d6
commit
16f187e7fa
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@ -63,8 +63,8 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.assertEqual(user_led.width, 1)
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self.assertEqual(user_led.dir, "o")
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pins = list(self.cm.iter_pins())
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(pin, port, buffer), = pins
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(pin, port, buffer), = self.cm.iter_pins()
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buffer._MustUse__silence = True
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self.assertIs(pin, user_led)
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self.assertEqual(port.io.name, "user_led_0__io")
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@ -77,12 +77,18 @@ class ResourceManagerTestCase(FHDLTestCase):
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i2c = self.cm.request("i2c", 0, dir={"sda": "o"})
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self.assertIsInstance(flipped(i2c.sda), Pin)
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self.assertEqual(i2c.sda.dir, "o")
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((_, _, scl_buffer), (_, _, sda_buffer)) = self.cm.iter_pins()
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scl_buffer._MustUse__silence = True
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sda_buffer._MustUse__silence = True
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def test_request_tristate(self):
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i2c = self.cm.request("i2c", 0)
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self.assertEqual(i2c.sda.dir, "io")
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((scl_pin, scl_port, _), (sda_pin, sda_port, _)) = self.cm.iter_pins()
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((scl_pin, scl_port, scl_buffer), (sda_pin, sda_port, sda_buffer)) = self.cm.iter_pins()
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scl_buffer._MustUse__silence = True
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sda_buffer._MustUse__silence = True
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self.assertIs(scl_pin, i2c.scl)
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self.assertIs(sda_pin, i2c.sda)
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self.assertEqual(scl_port.io.name, "i2c_0__scl__io")
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@ -96,7 +102,9 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.assertEqual(clk100.dir, "i")
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self.assertEqual(clk100.width, 1)
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(clk100_pin, clk100_port, _), = self.cm.iter_pins()
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(clk100_pin, clk100_port, buffer), = self.cm.iter_pins()
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buffer._MustUse__silence = True
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self.assertIs(clk100_pin, clk100)
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self.assertEqual(clk100_port.p.name, "clk100_0__p")
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self.assertEqual(clk100_port.p.width, clk100.width)
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@ -115,9 +123,11 @@ class ResourceManagerTestCase(FHDLTestCase):
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cs = self.cm.request("cs")
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clk = self.cm.request("clk")
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(
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(cs_pin, cs_port, _),
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(clk_pin, clk_port, _),
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(cs_pin, cs_port, cs_buffer),
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(clk_pin, clk_port, clk_buffer),
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) = self.cm.iter_pins()
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cs_buffer._MustUse__silence = True
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clk_buffer._MustUse__silence = True
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self.assertIs(cs_pin, cs)
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self.assertEqual(cs_port.invert, (True,))
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@ -138,27 +148,31 @@ class ResourceManagerTestCase(FHDLTestCase):
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def test_request_via_connector(self):
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self.cm.add_resources([
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Resource("spi", 0,
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Subsignal("ss", Pins("1", conn=("pmod", 0))),
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Subsignal("cs", Pins("1", conn=("pmod", 0))),
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Subsignal("clk", Pins("2", conn=("pmod", 0))),
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Subsignal("miso", Pins("3", conn=("pmod", 0))),
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Subsignal("mosi", Pins("4", conn=("pmod", 0))),
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Subsignal("cipo", Pins("3", conn=("pmod", 0))),
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Subsignal("copi", Pins("4", conn=("pmod", 0))),
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)
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])
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spi0 = self.cm.request("spi", 0)
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(
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(ss_pin, ss_port, _),
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(clk_pin, clk_port, _),
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(miso_pin, miso_port, _),
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(mosi_pin, mosi_port, _),
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(cs_pin, cs_port, cs_buffer),
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(clk_pin, clk_port, clk_buffer),
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(cipo_pin, cipo_port, cipo_buffer),
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(copi_pin, copi_port, copi_buffer),
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) = self.cm.iter_pins()
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self.assertIs(ss_pin, spi0.ss)
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cs_buffer._MustUse__silence = True
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clk_buffer._MustUse__silence = True
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cipo_buffer._MustUse__silence = True
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copi_buffer._MustUse__silence = True
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self.assertIs(cs_pin, spi0.cs)
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self.assertIs(clk_pin, spi0.clk)
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self.assertIs(miso_pin, spi0.miso)
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self.assertIs(mosi_pin, spi0.mosi)
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self.assertEqual(ss_port.io.metadata[0].name, "B0")
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self.assertIs(cipo_pin, spi0.cipo)
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self.assertIs(copi_pin, spi0.copi)
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self.assertEqual(cs_port.io.metadata[0].name, "B0")
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self.assertEqual(clk_port.io.metadata[0].name, "B1")
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self.assertEqual(miso_port.io.metadata[0].name, "B2")
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self.assertEqual(mosi_port.io.metadata[0].name, "B3")
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self.assertEqual(cipo_port.io.metadata[0].name, "B2")
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self.assertEqual(copi_port.io.metadata[0].name, "B3")
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def test_request_via_nested_connector(self):
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new_connectors = [
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@ -167,35 +181,41 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.cm.add_connectors(new_connectors)
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self.cm.add_resources([
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Resource("spi", 0,
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Subsignal("ss", Pins("1", conn=("pmod_extension", 0))),
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Subsignal("cs", Pins("1", conn=("pmod_extension", 0))),
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Subsignal("clk", Pins("2", conn=("pmod_extension", 0))),
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Subsignal("miso", Pins("3", conn=("pmod_extension", 0))),
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Subsignal("mosi", Pins("4", conn=("pmod_extension", 0))),
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Subsignal("cipo", Pins("3", conn=("pmod_extension", 0))),
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Subsignal("copi", Pins("4", conn=("pmod_extension", 0))),
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)
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])
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spi0 = self.cm.request("spi", 0)
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(
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(ss_pin, ss_port, _),
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(clk_pin, clk_port, _),
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(miso_pin, miso_port, _),
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(mosi_pin, mosi_port, _),
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(cs_pin, cs_port, cs_buffer),
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(clk_pin, clk_port, clk_buffer),
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(cipo_pin, cipo_port, cipo_buffer),
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(copi_pin, copi_port, copi_buffer),
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) = self.cm.iter_pins()
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self.assertIs(ss_pin, spi0.ss)
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cs_buffer._MustUse__silence = True
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clk_buffer._MustUse__silence = True
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cipo_buffer._MustUse__silence = True
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copi_buffer._MustUse__silence = True
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self.assertIs(cs_pin, spi0.cs)
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self.assertIs(clk_pin, spi0.clk)
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self.assertIs(miso_pin, spi0.miso)
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self.assertIs(mosi_pin, spi0.mosi)
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self.assertEqual(ss_port.io.metadata[0].name, "B0")
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self.assertIs(cipo_pin, spi0.cipo)
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self.assertIs(copi_pin, spi0.copi)
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self.assertEqual(cs_port.io.metadata[0].name, "B0")
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self.assertEqual(clk_port.io.metadata[0].name, "B1")
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self.assertEqual(miso_port.io.metadata[0].name, "B2")
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self.assertEqual(mosi_port.io.metadata[0].name, "B3")
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self.assertEqual(cipo_port.io.metadata[0].name, "B2")
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self.assertEqual(copi_port.io.metadata[0].name, "B3")
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def test_request_clock(self):
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clk100 = self.cm.request("clk100", 0)
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clk50 = self.cm.request("clk50", 0, dir="i")
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(
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(clk100_pin, clk100_port, _),
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(clk50_pin, clk50_port, _),
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(clk100_pin, clk100_port, clk100_buffer),
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(clk50_pin, clk50_port, clk50_buffer),
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) = self.cm.iter_pins()
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clk100_buffer._MustUse__silence = True
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clk50_buffer._MustUse__silence = True
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self.assertEqual(list(self.cm.iter_clock_constraints()), [
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(clk100.i, clk100_port.p, 100e6),
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(clk50.i, clk50_port.io, 50e6)
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@ -207,6 +227,9 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.assertEqual(list(self.cm.iter_clock_constraints()), [
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(i2c.scl.o, None, 100e3)
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])
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((_, _, scl_buffer), (_, _, sda_buffer)) = self.cm.iter_pins()
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scl_buffer._MustUse__silence = True
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sda_buffer._MustUse__silence = True
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def test_wrong_resources(self):
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with self.assertRaisesRegex(TypeError, r"^Object 'wrong' is not a Resource$"):
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@ -244,16 +267,20 @@ class ResourceManagerTestCase(FHDLTestCase):
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self.cm.add_clock_constraint(Signal(), None)
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def test_wrong_request_duplicate(self):
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self.cm.request("user_led", 0)
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(pin, port, buffer), = self.cm.iter_pins()
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buffer._MustUse__silence = True
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with self.assertRaisesRegex(ResourceError,
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r"^Resource user_led#0 has already been requested$"):
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self.cm.request("user_led", 0)
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self.cm.request("user_led", 0)
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def test_wrong_request_duplicate_physical(self):
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self.cm.add_resources([
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Resource("clk20", 0, Pins("H1", dir="i")),
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])
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self.cm.request("clk100", 0)
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(pin, port, buffer), = self.cm.iter_pins()
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buffer._MustUse__silence = True
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with self.assertRaisesRegex(ResourceError,
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(r"^Resource component clk20_0 uses physical pin H1, but it is already "
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r"used by resource component clk100_0 that was requested earlier$")):
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@ -293,6 +320,8 @@ class ResourceManagerTestCase(FHDLTestCase):
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def test_wrong_clock_constraint_twice(self):
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clk100 = self.cm.request("clk100")
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(pin, port, buffer), = self.cm.iter_pins()
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buffer._MustUse__silence = True
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with self.assertRaisesRegex(ValueError,
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(r"^Cannot add clock constraint on \(sig clk100_0__i\), which is already "
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r"constrained to 100000000\.0 Hz$")):
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