hdl._ir: Fix fallout from #1190, add more tests.
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@ -772,7 +772,7 @@ class NetlistEmitter:
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signal, bit = self.late_net_to_signal[left]
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other_src_loc = self.connect_src_loc[left]
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raise _ir.DriverConflict(f"Bit {bit} of signal {signal!r} has multiple drivers: "
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f"{other_src_loc} and {src_loc}")
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f"{other_src_loc[0]}:{other_src_loc[1]} and {src_loc[0]}:{src_loc[1]}")
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self.netlist.connections[left] = right
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self.connect_src_loc[left] = src_loc
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@ -785,15 +785,15 @@ class NetlistEmitter:
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domain_name = cd.name if cd is not None else "comb"
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other_domain_name = driver.domain.name if driver.domain is not None else "comb"
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raise _ir.DriverConflict(
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f"Signal {lhs} driven from domain {domain_name} at {src_loc} and domain "
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f"{other_domain_name} at {driver.src_loc}")
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f"Signal {lhs!r} driven from domain {domain_name} at {src_loc[0]}:{src_loc[1]} and domain "
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f"{other_domain_name} at {driver.src_loc[0]}:{driver.src_loc[1]}")
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if driver.module_idx != module_idx:
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mod_name = ".".join(self.netlist.modules[module_idx].name or ("<toplevel>",))
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other_mod_name = \
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".".join(self.netlist.modules[driver.module_idx].name or ("<toplevel>",))
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raise _ir.DriverConflict(
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f"Signal {lhs} driven from module {mod_name} at {src_loc} and "
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f"module {other_mod_name} at {driver.src_loc}")
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f"Signal {lhs!r} driven from module {mod_name} at {src_loc[0]}:{src_loc[1]} and "
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f"module {other_mod_name} at {driver.src_loc[0]}:{driver.src_loc[1]}")
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else:
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driver = NetlistDriver(module_idx, lhs, domain=cd, src_loc=src_loc)
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self.drivers[lhs] = driver
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@ -1,4 +1,4 @@
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# amaranth: UnusedPrint=no, UnusedProperty
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# amaranth: UnusedPrint=no, UnusedProperty=no
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import warnings
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from enum import Enum, EnumMeta
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@ -3142,3 +3142,40 @@ class SwitchTestCase(FHDLTestCase):
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(cell 21 0 (cover 0.6 20.0 neg 0.12 ('c')))
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)
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""")
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class ConflictTestCase(FHDLTestCase):
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def test_domain_conflict(self):
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s = Signal()
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m = Module()
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m.d.sync += s.eq(1)
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m1 = Module()
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m1.d.comb += s.eq(2)
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m.submodules.m1 = m1
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with self.assertRaisesRegex(DriverConflict,
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r"^Signal \(sig s\) driven from domain comb at "
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r".*test_hdl_ir.py:\d+ and domain sync at "
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r".*test_hdl_ir.py:\d+$"):
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build_netlist(Fragment.get(m, None), [])
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def test_module_conflict(self):
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s = Signal()
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m = Module()
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m.d.sync += s.eq(1)
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m1 = Module()
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m1.d.sync += s.eq(2)
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m.submodules.m1 = m1
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with self.assertRaisesRegex(DriverConflict,
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r"^Signal \(sig s\) driven from module top\.m1 at "
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r".*test_hdl_ir.py:\d+ and module top at "
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r".*test_hdl_ir.py:\d+$"):
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build_netlist(Fragment.get(m, None), [])
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def test_instance_conflict(self):
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s = Signal()
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m = Module()
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m.d.sync += s.eq(1)
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m.submodules.t = Instance("tt", o_s=s)
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with self.assertRaisesRegex(DriverConflict,
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r"^Bit 0 of signal \(sig s\) has multiple drivers: "
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r".*test_hdl_ir.py:\d+ and .*test_hdl_ir.py:\d+$"):
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build_netlist(Fragment.get(m, None), [])
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