test_lib_crc: speed up tests using multiprocessing.

tests/test_lib_crc.py

@@ -1,6 +1,7 @@
 # amaranth: UnusedElaboratable=no
 
 import unittest
+import concurrent.futures
 
 from amaranth.sim import *
 from amaranth.lib.crc import Algorithm, Processor, catalog
@@ -229,12 +230,14 @@ class CRCTestCase(unittest.TestCase):
             crc = catalog.CRC8_AUTOSAR()
             crc.compute([3, 4, 256])
 
-    def test_crc_bytes(self):
+    def for_each_crc_concurrent(self, f):
-        """
+        with concurrent.futures.ProcessPoolExecutor() as executor:
-        Verify CRC generation by computing the check value for each CRC
+            futures = {executor.submit(f, crc) for crc in CRCS}
-        in the catalogue with byte-sized inputs.
+            for future in concurrent.futures.as_completed(futures):
-        """
+                future.result()
-        for name in CRCS:
+
+    @staticmethod
+    def perform_test_crc_bytes(name):
         crc = getattr(catalog, name)(data_width=8).create()
         check = CRC_CHECKS[name][0]
 
@@ -246,18 +249,22 @@ class CRCTestCase(unittest.TestCase):
                 yield Tick()
             yield crc.valid.eq(0)
             yield Tick()
-                self.assertEqual((yield crc.crc), check)
+            assert (yield crc.crc) == check
 
         sim = Simulator(crc)
         sim.add_testbench(process)
         sim.add_clock(1e-6)
         sim.run()
 
-    def test_crc_words(self):
+    def test_crc_bytes(self):
         """
-        Verify CRC generation for non-byte-sized data by computing a check
+        Verify CRC generation by computing the check value for each CRC
-        value for 1, 2, 4, 16, 32, and 64-bit inputs.
+        in the catalogue with byte-sized inputs.
         """
+        self.for_each_crc_concurrent(self.perform_test_crc_bytes)
+
+    @staticmethod
+    def perform_test_crc_words(name):
         # We can't use the catalogue check value since it requires 8-bit
         # inputs, so we'll instead use an input of b"12345678".
         data = b"12345678"
@@ -267,7 +274,6 @@ class CRCTestCase(unittest.TestCase):
         bits = "".join(f"{x:08b}" for x in data)
         bits_r = "".join(f"{x:08b}"[::-1] for x in data)
 
-        for name in CRCS:
         for m in (1, 2, 4, 16, 32, 64):
             algo = getattr(catalog, name)
             crc = algo(data_width=m).create()
@@ -291,16 +297,22 @@ class CRCTestCase(unittest.TestCase):
                     yield Tick()
                 yield crc.valid.eq(0)
                 yield Tick()
-                    self.assertEqual((yield crc.crc), check)
+                assert (yield crc.crc) == check
 
             sim = Simulator(crc)
             sim.add_testbench(process)
             sim.add_clock(1e-6)
             sim.run()
 
-    def test_crc_match(self):
+    def test_crc_words(self):
-        """Verify match_detected output detects valid codewords."""
+        """
-        for name in CRCS:
+        Verify CRC generation for non-byte-sized data by computing a check
+        value for 1, 2, 4, 16, 32, and 64-bit inputs.
+        """
+        self.for_each_crc_concurrent(self.perform_test_crc_words)
+
+    @staticmethod
+    def perform_test_crc_match(name):
         algo = getattr(catalog, name)
         n = algo.crc_width
         m = 8 if n % 8 == 0 else 1
@@ -342,9 +354,13 @@ class CRCTestCase(unittest.TestCase):
                 yield Tick()
             yield crc.valid.eq(0)
             yield Tick()
-                self.assertTrue((yield crc.match_detected))
+            assert (yield crc.match_detected)
 
         sim = Simulator(crc)
         sim.add_testbench(process)
         sim.add_clock(1e-6)
         sim.run()
+
+    def test_crc_match(self):
+        """Verify match_detected output detects valid codewords."""
+        self.for_each_crc_concurrent(self.perform_test_crc_match)