vendor._altera: implement lib.io buffer primitives.
This commit is contained in:
Wanda
Catherine
parent
7dd93bea57
commit
1b9290188b
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@ -1,9 +1,184 @@
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from abc import abstractmethod
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from ..hdl import *
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from ..hdl import _ast
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from ..lib import io, wiring
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from ..build import *
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# The altiobuf_* and altddio_* primitives are explained in the following Intel documents:
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# * https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altiobuf.pdf
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# * https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altddio.pdf
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# See also errata mentioned in: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd11192012_735.html.
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# Horrible hack here. To get Quartus to pack FFs into IOEs, the port needs to have an
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# ``useioff`` attribute. Unfortunately, this means that FF packing can only be controlled
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# with port granularity, not bit granularity. However, Quartus doesn't seem to mind
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# this attribute being set when it's not possible to pack a FF — it's just ignored with
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# a warning. So, we just set it on whatever is passed to ``FFBuffer`` — at worst, we'll
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# cause some extra random FFs to be opportunistically packed into the IOE for other bits
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# of a sliced port.
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#
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# This function is also used by ``DDRBuffer`` to pack the output enable FF.
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def _add_useioff(value):
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if isinstance(value, _ast.IOPort):
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value.attrs["useioff"] = 1
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elif isinstance(value, _ast.IOConcat):
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for part in value.parts:
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_add_useioff(part)
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elif isinstance(value, _ast.IOSlice):
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_add_useioff(value.value)
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else:
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raise NotImplementedError # :nocov:
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class InnerBuffer(wiring.Component):
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"""A private component used to implement ``lib.io`` buffers.
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Works like ``lib.io.Buffer``, with the following differences:
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- ``port.invert`` is ignored (handling the inversion is the outer buffer's responsibility)
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- output enable is per-pin
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"""
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def __init__(self, direction, port, *, useioff=False):
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self.direction = direction
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self.port = port
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members = {}
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if direction is not io.Direction.Output:
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members["i"] = wiring.In(len(port))
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if direction is not io.Direction.Input:
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members["o"] = wiring.Out(len(port))
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members["oe"] = wiring.Out(len(port))
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super().__init__(wiring.Signature(members).flip())
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if useioff:
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if isinstance(port, io.SingleEndedPort):
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_add_useioff(port.io)
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elif isinstance(port, io.DifferentialPort):
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_add_useioff(port.p)
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_add_useioff(port.n)
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def elaborate(self, platform):
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kwargs = dict(
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p_enable_bus_hold="FALSE",
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p_number_of_channels=len(self.port),
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)
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if isinstance(self.port, io.SingleEndedPort):
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kwargs["p_use_differential_mode"] = "FALSE"
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elif isinstance(self.port, io.DifferentialPort):
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kwargs["p_use_differential_mode"] = "TRUE"
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else:
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raise TypeError(f"Unknown port type {self.port!r}")
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if self.direction is io.Direction.Input:
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if isinstance(self.port, io.SingleEndedPort):
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kwargs["i_datain"] = self.port.io
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else:
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kwargs["i_datain"] = self.port.p,
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kwargs["i_datain_b"] = self.port.n,
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return Instance("altiobuf_in",
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o_dataout=self.i,
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**kwargs,
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)
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elif self.direction is io.Direction.Output:
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if isinstance(self.port, io.SingleEndedPort):
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kwargs["o_dataout"] = self.port.io
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else:
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kwargs["o_dataout"] = self.port.p,
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kwargs["o_dataout_b"] = self.port.n,
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return Instance("altiobuf_out",
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p_use_oe="TRUE",
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i_datain=self.o,
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i_oe=self.oe,
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**kwargs,
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)
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elif self.direction is io.Direction.Bidir:
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if isinstance(self.port, io.SingleEndedPort):
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kwargs["io_dataio"] = self.port.io
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else:
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kwargs["io_dataio"] = self.port.p,
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kwargs["io_dataio_b"] = self.port.n,
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return Instance("altiobuf_bidir",
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i_datain=self.o,
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i_oe=self.oe,
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o_dataout=self.i,
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**kwargs,
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)
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else:
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assert False # :nocov:
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class IOBuffer(io.Buffer):
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def elaborate(self, platform):
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m = Module()
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m.submodules.buf = buf = InnerBuffer(self.direction, self.port)
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inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
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if self.direction is not io.Direction.Output:
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m.d.comb += self.i.eq(buf.i ^ inv_mask)
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if self.direction is not io.Direction.Input:
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m.d.comb += buf.o.eq(self.o ^ inv_mask)
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m.d.comb += buf.oe.eq(self.oe.replicate(len(self.port)))
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return m
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class FFBuffer(io.FFBuffer):
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def elaborate(self, platform):
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m = Module()
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m.submodules.buf = buf = InnerBuffer(self.direction, self.port, useioff=True)
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inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
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if self.direction is not io.Direction.Output:
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i_inv = Signal.like(self.i)
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m.d[self.i_domain] += i_inv.eq(buf.i)
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m.d.comb += self.i.eq(i_inv ^ inv_mask)
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if self.direction is not io.Direction.Input:
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m.d[self.o_domain] += buf.o.eq(self.o ^ inv_mask)
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m.d[self.o_domain] += buf.oe.eq(self.oe.replicate(len(self.port)))
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return m
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class DDRBuffer(io.DDRBuffer):
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def elaborate(self, platform):
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m = Module()
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m.submodules.buf = buf = InnerBuffer(self.direction, self.port, useioff=True)
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inv_mask = sum(inv << bit for bit, inv in enumerate(self.port.invert))
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if self.direction is not io.Direction.Output:
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i0_reg = Signal(len(self.port))
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i0_inv = Signal(len(self.port))
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i1_inv = Signal(len(self.port))
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m.submodules.i_ddr = Instance("altddio_in",
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p_width=len(self.port),
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i_datain=buf.i,
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i_inclock=ClockSignal(self.i_domain),
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o_dataout_h=i0_inv,
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o_dataout_l=i1_inv,
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)
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m.d[self.i_domain] += i0_reg.eq(i0_inv)
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m.d.comb += self.i[0].eq(i0_reg ^ inv_mask)
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m.d.comb += self.i[1].eq(i1_inv ^ inv_mask)
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if self.direction is not io.Direction.Input:
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m.submodules.o_ddr = Instance("altddio_out",
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p_width=len(self.port),
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o_dataout=buf.o,
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i_outclock=ClockSignal(self.o_domain),
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i_datain_h=self.o[0] ^ inv_mask,
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i_datain_l=self.o[1] ^ inv_mask,
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)
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m.d[self.o_domain] += buf.oe.eq(self.oe.replicate(len(self.port)))
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return m
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class AlteraPlatform(TemplatedPlatform):
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"""
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.. rubric:: Quartus toolchain
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@ -67,6 +242,9 @@ class AlteraPlatform(TemplatedPlatform):
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10935, # Verilog casex/casez overlaps with a previous casex/vasez item expression
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12125, # Using design file which is not specified as a design file for the current project, but contains definitions used in project
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18236, # Number of processors not specified in QSF
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176225, # Can't pack node <node> to I/O pin
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176250, # Ignoring invalid fast I/O register assignments.
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176272, # Can't pack node <node> and I/O cell
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292013, # Feature is only available with a valid subscription license
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]
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@ -293,247 +471,21 @@ class AlteraPlatform(TemplatedPlatform):
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else:
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return super().create_missing_domain(name)
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# The altiobuf_* and altddio_* primitives are explained in the following Intel documents:
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# * https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altiobuf.pdf
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# * https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altddio.pdf
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# See also errata mentioned in: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd11192012_735.html.
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@staticmethod
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def _get_ireg(m, pin, invert):
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def get_ineg(i):
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if invert:
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i_neg = Signal.like(i, name_suffix="_neg")
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m.d.comb += i.eq(~i_neg)
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return i_neg
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else:
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return i
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if pin.xdr == 0:
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return get_ineg(pin.i)
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elif pin.xdr == 1:
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i_sdr = Signal(pin.width, name="{}_i_sdr")
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i_neg = get_ineg(pin.i)
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for bit in range(pin.width):
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m.submodules += Instance("dff",
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i_clk=pin.i_clk,
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i_d=i_sdr[bit],
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o_q=i_neg[bit],
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o_clrn=Const(1),
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o_prn=Const(1),
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)
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return i_sdr
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elif pin.xdr == 2:
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i_ddr = Signal(pin.width, name=f"{pin.name}_i_ddr")
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m.submodules[f"{pin.name}_i_ddr"] = Instance("altddio_in",
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p_width=pin.width,
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i_datain=i_ddr,
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i_inclock=pin.i_clk,
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o_dataout_h=get_ineg(pin.i0),
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o_dataout_l=get_ineg(pin.i1),
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)
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return i_ddr
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assert False
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@staticmethod
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def _get_oreg(m, pin, invert):
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def get_oneg(o):
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if invert:
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o_neg = Signal.like(o, name_suffix="_neg")
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m.d.comb += o_neg.eq(~o)
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return o_neg
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else:
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return o
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if pin.xdr == 0:
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return get_oneg(pin.o)
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elif pin.xdr == 1:
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o_sdr = Signal(pin.width, name=f"{pin.name}_o_sdr")
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for bit in range(pin.width):
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o_neg = get_oneg(pin.o)
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m.submodules += Instance("dff",
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i_clk=pin.o_clk,
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i_d=o_neg[bit],
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o_q=o_sdr[bit],
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o_clrn=Const(1),
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o_prn=Const(1),
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)
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return o_sdr
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elif pin.xdr == 2:
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o_ddr = Signal(pin.width, name=f"{pin.name}_o_ddr")
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m.submodules[f"{pin.name}_o_ddr"] = Instance("altddio_out",
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p_width=pin.width,
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o_dataout=o_ddr,
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i_outclock=pin.o_clk,
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i_datain_h=get_oneg(pin.o0),
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i_datain_l=get_oneg(pin.o1),
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)
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return o_ddr
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assert False
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@staticmethod
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def _get_oereg(m, pin):
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# altiobuf_ requires an output enable signal for each pin, but pin.oe is 1 bit wide.
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if pin.xdr == 0:
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return pin.oe.replicate(pin.width)
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elif pin.xdr in (1, 2):
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oe_reg = Signal(pin.width, name=f"{pin.name}_oe_reg")
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oe_reg.attrs["useioff"] = "1"
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for bit in range(pin.width):
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m.submodules += Instance("dff",
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i_clk=pin.o_clk,
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i_d=pin.oe,
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o_q=oe_reg[bit],
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o_clrn=Const(1),
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o_prn=Const(1),
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)
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return oe_reg
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assert False
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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if pin.xdr == 1:
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port.attrs["useioff"] = 1
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m = Module()
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m.submodules[pin.name] = Instance("altiobuf_in",
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p_enable_bus_hold="FALSE",
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p_number_of_channels=pin.width,
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p_use_differential_mode="FALSE",
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i_datain=port.io,
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o_dataout=self._get_ireg(m, pin, invert)
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)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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if pin.xdr == 1:
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port.attrs["useioff"] = 1
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m = Module()
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m.submodules[pin.name] = Instance("altiobuf_out",
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p_enable_bus_hold="FALSE",
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p_number_of_channels=pin.width,
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p_use_differential_mode="FALSE",
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p_use_oe="FALSE",
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i_datain=self._get_oreg(m, pin, invert),
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o_dataout=port.io,
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)
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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if pin.xdr == 1:
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port.attrs["useioff"] = 1
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m = Module()
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m.submodules[pin.name] = Instance("altiobuf_out",
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p_enable_bus_hold="FALSE",
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p_number_of_channels=pin.width,
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p_use_differential_mode="FALSE",
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p_use_oe="TRUE",
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i_datain=self._get_oreg(m, pin, invert),
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o_dataout=port.io,
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i_oe=self._get_oereg(m, pin)
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)
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return m
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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if pin.xdr == 1:
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port.attrs["useioff"] = 1
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m = Module()
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m.submodules[pin.name] = Instance("altiobuf_bidir",
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p_enable_bus_hold="FALSE",
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p_number_of_channels=pin.width,
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p_use_differential_mode="FALSE",
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i_datain=self._get_oreg(m, pin, invert),
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io_dataio=port.io,
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o_dataout=self._get_ireg(m, pin, invert),
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i_oe=self._get_oereg(m, pin),
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)
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return m
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def get_diff_input(self, pin, port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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if pin.xdr == 1:
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port.p.attrs["useioff"] = 1
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port.n.attrs["useioff"] = 1
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m = Module()
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m.submodules[pin.name] = Instance("altiobuf_in",
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p_enable_bus_hold="FALSE",
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p_number_of_channels=pin.width,
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p_use_differential_mode="TRUE",
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i_datain=port.p,
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i_datain_b=port.n,
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o_dataout=self._get_ireg(m, pin, invert)
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)
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return m
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def get_diff_output(self, pin, port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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if pin.xdr == 1:
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port.p.attrs["useioff"] = 1
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port.n.attrs["useioff"] = 1
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m = Module()
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m.submodules[pin.name] = Instance("altiobuf_out",
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p_enable_bus_hold="FALSE",
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p_number_of_channels=pin.width,
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p_use_differential_mode="TRUE",
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p_use_oe="FALSE",
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i_datain=self._get_oreg(m, pin, invert),
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o_dataout=port.p,
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o_dataout_b=port.n,
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)
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return m
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def get_diff_tristate(self, pin, port, attrs, invert):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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if pin.xdr == 1:
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port.p.attrs["useioff"] = 1
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port.n.attrs["useioff"] = 1
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m = Module()
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m.submodules[pin.name] = Instance("altiobuf_out",
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p_enable_bus_hold="FALSE",
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p_number_of_channels=pin.width,
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p_use_differential_mode="TRUE",
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p_use_oe="TRUE",
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i_datain=self._get_oreg(m, pin, invert),
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o_dataout=port.p,
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o_dataout_b=port.n,
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i_oe=self._get_oereg(m, pin),
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)
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return m
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def get_diff_input_output(self, pin, port, attrs, invert):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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if pin.xdr == 1:
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port.p.attrs["useioff"] = 1
|
||||
port.n.attrs["useioff"] = 1
|
||||
|
||||
m = Module()
|
||||
m.submodules[pin.name] = Instance("altiobuf_bidir",
|
||||
p_enable_bus_hold="FALSE",
|
||||
p_number_of_channels=pin.width,
|
||||
p_use_differential_mode="TRUE",
|
||||
i_datain=self._get_oreg(m, pin, invert),
|
||||
io_dataio=port.p,
|
||||
io_dataio_b=port.n,
|
||||
o_dataout=self._get_ireg(m, pin, invert),
|
||||
i_oe=self._get_oereg(m, pin),
|
||||
)
|
||||
return m
|
||||
def get_io_buffer(self, buffer):
|
||||
if isinstance(buffer, io.Buffer):
|
||||
result = IOBuffer(buffer.direction, buffer.port)
|
||||
elif isinstance(buffer, io.FFBuffer):
|
||||
result = FFBuffer(buffer.direction, buffer.port)
|
||||
elif isinstance(buffer, io.DDRBuffer):
|
||||
result = DDRBuffer(buffer.direction, buffer.port)
|
||||
else:
|
||||
raise TypeError(f"Unsupported buffer type {buffer!r}") # :nocov:
|
||||
if buffer.direction is not io.Direction.Output:
|
||||
result.i = buffer.i
|
||||
if buffer.direction is not io.Direction.Input:
|
||||
result.o = buffer.o
|
||||
result.oe = buffer.oe
|
||||
return result
|
||||
|
||||
# The altera_std_synchronizer{,_bundle} megafunctions embed SDC constraints that mark false
|
||||
# paths, so use them instead of our default implementation.
|
||||
|
|
|
|||
Loading…
Reference in a new issue