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back.rtlil: Remove code allowing internal yosys cells in Instance.

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This was allowed only because Amaranth used it internally. Now that
all uses are gone, let's just disallow it entirely.
This commit is contained in:
Wanda 2024-02-27 11:20:33 +01:00 committed by Catherine
parent 6dc7c2718c
commit 1cb9d43841
1 changed files with 2 additions and 6 deletions
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8
amaranth/back/rtlil.py
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@ -923,12 +923,8 @@ class ModuleEmitter:
ports[name] = self.instance_wires[cell_idx, name] ports[name] = self.instance_wires[cell_idx, name]
for name, nets in cell.ports_io.items(): for name, nets in cell.ports_io.items():
ports[name] = self.sigspec(nets) ports[name] = self.sigspec(nets)
if cell.type.startswith("$"): self.builder.cell(f"\\{cell.type}", cell.name, ports=ports, params=cell.parameters,
type = cell.type attrs=cell.attributes, src=_src(cell.src_loc))
else:
type = "\\" + cell.type
self.builder.cell(type, cell.name, ports=ports, params=cell.parameters,
attrs=cell.attributes, src=_src(cell.src_loc))
def emit_cells(self): def emit_cells(self):
for cell_idx in self.module.cells: for cell_idx in self.module.cells: