hdl: remove subclassing of AnyValue and Property.
This subclassing is unnecessary and makes downstream code more complex. In the new IR, they are unified into cells with the same name anyway. Even before that, this change simplifies things.
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5 changed files with 78 additions and 141 deletions
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@ -442,27 +442,13 @@ class _RHSValueCompiler(_ValueCompiler):
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def on_Const(self, value):
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return _const(value)
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def on_AnyConst(self, value):
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def on_AnyValue(self, value):
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if value in self.s.anys:
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return self.s.anys[value]
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res_shape = value.shape()
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res = self.s.rtlil.wire(width=res_shape.width, src=_src(value.src_loc))
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self.s.rtlil.cell("$anyconst", ports={
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"\\Y": res,
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}, params={
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"WIDTH": res_shape.width,
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}, src=_src(value.src_loc))
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self.s.anys[value] = res
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return res
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def on_AnySeq(self, value):
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if value in self.s.anys:
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return self.s.anys[value]
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res_shape = value.shape()
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res = self.s.rtlil.wire(width=res_shape.width, src=_src(value.src_loc))
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self.s.rtlil.cell("$anyseq", ports={
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self.s.rtlil.cell("$" + value.kind.value, ports={
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"\\Y": res,
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}, params={
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"WIDTH": res_shape.width,
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@ -619,10 +605,7 @@ class _LHSValueCompiler(_ValueCompiler):
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def on_Const(self, value):
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raise TypeError # :nocov:
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def on_AnyConst(self, value):
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raise TypeError # :nocov:
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def on_AnySeq(self, value):
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def on_AnyValue(self, value):
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raise TypeError # :nocov:
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def on_Initial(self, value):
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@ -721,21 +704,17 @@ class _StatementCompiler(_xfrm.StatementVisitor):
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else:
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self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)
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def on_property(self, stmt):
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def on_Property(self, stmt):
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self(stmt._check.eq(stmt.test))
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self(stmt._en.eq(1))
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en_wire = self.rhs_compiler(stmt._en)
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check_wire = self.rhs_compiler(stmt._check)
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self.state.rtlil.cell("$" + stmt._kind, ports={
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self.state.rtlil.cell("$" + stmt.kind.value, ports={
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"\\A": check_wire,
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"\\EN": en_wire,
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}, src=_src(stmt.src_loc), name=stmt.name)
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on_Assert = on_property
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on_Assume = on_property
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on_Cover = on_property
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def on_Switch(self, stmt):
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self._check_rhs(stmt.test)
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