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back.pysim: Reuse clock simulation commands

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This commit is contained in:
Stuart Olsen 2020-04-06 22:22:09 -07:00 committed by whitequark
parent bb1bbcc51a
commit 2398b7922e
1 changed files with 7 additions and 4 deletions
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11
nmigen/back/pysim.py
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@ -1021,11 +1021,14 @@ class Simulator:
# Behave correctly if the process is added after the clock signal is manipulated, or if # Behave correctly if the process is added after the clock signal is manipulated, or if
# its reset state is high. # its reset state is high.
initial = (yield domain.clk) initial = (yield domain.clk)
steps = (
domain.clk.eq(~initial),
Delay(half_period),
domain.clk.eq(initial),
Delay(half_period),
)
while True: while True:
yield domain.clk.eq(~initial) yield from iter(steps)
yield Delay(half_period)
yield domain.clk.eq(initial)
yield Delay(half_period)
self._add_coroutine_process(clk_process, default_cmd=None) self._add_coroutine_process(clk_process, default_cmd=None)
self._clocked.add(domain) self._clocked.add(domain)