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lib.memory: Add Signature.create implementations.

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Wanda 2024-03-16 00:37:53 +01:00 • committed by Catherine
parent 83701d74cf
commit 23f1b63425
2 changed files with 28 additions and 4 deletions
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18
tests/test_lib_memory.py
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@ -122,6 +122,15 @@ class WritePortTestCase(FHDLTestCase):
self.assertIs(port.memory, m)
self.assertEqual(m.w_ports, (port,))
signature = memory.WritePort.Signature(shape=MyStruct, addr_width=4)
port = signature.create()
self.assertEqual(port.signature, signature)
self.assertIsNone(port.memory)
self.assertEqual(port.domain, "sync")
self.assertRepr(port.addr, "(sig port__addr)")
port = signature.create(path=("abc",))
self.assertRepr(port.addr, "(sig abc__addr)")
def test_constructor_wrong(self):
signature = memory.ReadPort.Signature(shape=8, addr_width=4)
with self.assertRaisesRegex(TypeError,
@ -224,6 +233,15 @@ class ReadPortTestCase(FHDLTestCase):
self.assertIs(port.memory, m)
self.assertEqual(port.transparent_for, (write_port,))
signature = memory.ReadPort.Signature(shape=MyStruct, addr_width=4)
port = signature.create()
self.assertEqual(port.signature, signature)
self.assertIsNone(port.memory)
self.assertEqual(port.domain, "sync")
self.assertRepr(port.addr, "(sig port__addr)")
port = signature.create(path=("abc",))
self.assertRepr(port.addr, "(sig abc__addr)")
def test_constructor_wrong(self):
signature = memory.WritePort.Signature(shape=8, addr_width=4)
with self.assertRaisesRegex(TypeError,