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back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.

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This commit is contained in:
whitequark 2018-12-14 10:57:13 +00:00
parent 7d91dd56c8
commit 240a40c2c2
1 changed files with 2 additions and 2 deletions
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4
nmigen/back/pysim.py
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@ -513,8 +513,8 @@ class Simulator:
for domain, cd in self._domains.items():
with gtkw_save.group("d.{}".format(domain)):
if cd.rst is not None:
gtkw_save.trace("top.{}".format(cd.rst.name))
gtkw_save.trace("top.{}".format(cd.clk.name))
gtkw_save.trace(self._vcd_names[cd.rst])
gtkw_save.trace(self._vcd_names[cd.clk])
for signal in self._gtkw_signals:
if signal in self._vcd_names: