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hdl.dsl: Support Assert and Assume where an Assign can occur.

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William D. Jones 2018-12-28 02:10:15 -05:00 • committed by whitequark
parent e6517a33c7
commit 2412650f56
3 changed files with 4 additions and 4 deletions
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2
nmigen/test/test_hdl_dsl.py
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@ -74,7 +74,7 @@ class DSLTestCase(FHDLTestCase):
def test_d_asgn_wrong(self):
m = Module()
with self.assertRaises(SyntaxError,
msg="Only assignments may be appended to d.sync"):
msg="Only assignments, asserts, and assumes may be appended to d.sync"):
m.d.sync += Switch(self.s1, {})
def test_comb_wrong(self):