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hdl.dsl: Support Assert and Assume where an Assign can occur.

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William D. Jones 2018-12-28 02:10:15 -05:00 committed by whitequark
parent e6517a33c7
commit 2412650f56
3 changed files with 4 additions and 4 deletions
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2
nmigen/__init__.py
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@ -1,4 +1,4 @@
from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal, Assert, Assume
from .hdl.dsl import Module from .hdl.dsl import Module
from .hdl.cd import ClockDomain from .hdl.cd import ClockDomain
from .hdl.ir import Fragment, Instance from .hdl.ir import Fragment, Instance

4
nmigen/hdl/dsl.py
View file

@ -336,9 +336,9 @@ class Module(_ModuleBuilderRoot):
self._pop_ctrl() self._pop_ctrl()
for assign in Statement.wrap(assigns): for assign in Statement.wrap(assigns):
if not compat_mode and not isinstance(assign, Assign): if not compat_mode and not isinstance(assign, (Assign, Assert, Assume)):
raise SyntaxError( raise SyntaxError(
"Only assignments may be appended to d.{}" "Only assignments, asserts, and assumes may be appended to d.{}"
.format(domain_name(domain))) .format(domain_name(domain)))
for signal in assign._lhs_signals(): for signal in assign._lhs_signals():

2
nmigen/test/test_hdl_dsl.py
View file

@ -74,7 +74,7 @@ class DSLTestCase(FHDLTestCase):
def test_d_asgn_wrong(self): def test_d_asgn_wrong(self):
m = Module() m = Module()
with self.assertRaises(SyntaxError, with self.assertRaises(SyntaxError,
msg="Only assignments may be appended to d.sync"): msg="Only assignments, asserts, and assumes may be appended to d.sync"):
m.d.sync += Switch(self.s1, {}) m.d.sync += Switch(self.s1, {})
def test_comb_wrong(self): def test_comb_wrong(self):