Implement RFC 43: Rename reset= to init=.

examples/basic/ctr.py

@@ -4,7 +4,7 @@ from amaranth.cli import main
 
 class Counter(Elaboratable):
     def __init__(self, width):
-        self.v = Signal(width, reset=2**width-1)
+        self.v = Signal(width, init=2**width-1)
         self.o = Signal()
 
     def elaborate(self, platform):

examples/basic/ctr_en.py

@@ -5,7 +5,7 @@ from amaranth.back import verilog
 
 class Counter(Elaboratable):
     def __init__(self, width):
-        self.v = Signal(width, reset=2**width-1)
+        self.v = Signal(width, init=2**width-1)
         self.o = Signal()
         self.en = Signal()
 

examples/basic/por.py

@@ -7,7 +7,7 @@ cd_por  = ClockDomain(reset_less=True)
 cd_sync = ClockDomain()
 m.domains += cd_por, cd_sync
 
-delay = Signal(range(256), reset=255)
+delay = Signal(range(256), init=255)
 with m.If(delay != 0):
     m.d.por += delay.eq(delay - 1)
 m.d.comb += [

examples/basic/uart.py

@@ -32,7 +32,7 @@ class UART(Elaboratable):
         m = Module()
 
         tx_phase = Signal(range(self.divisor))
-        tx_shreg = Signal(1 + self.data_bits + 1, reset=-1)
+        tx_shreg = Signal(1 + self.data_bits + 1, init=-1)
         tx_count = Signal(range(len(tx_shreg) + 1))
 
         m.d.comb += self.tx_o.eq(tx_shreg[0])
@@ -55,7 +55,7 @@ class UART(Elaboratable):
                 ]
 
         rx_phase = Signal(range(self.divisor))
-        rx_shreg = Signal(1 + self.data_bits + 1, reset=-1)
+        rx_shreg = Signal(1 + self.data_bits + 1, init=-1)
         rx_count = Signal(range(len(rx_shreg) + 1))
 
         m.d.comb += self.rx_data.eq(rx_shreg[1:-1])