Implement RFC 43: Rename reset= to init=.
This commit is contained in:
Wanda
Catherine
parent
b30c87fa3e
commit
24a392887a
30 changed files with 476 additions and 276 deletions
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@ -1140,24 +1140,26 @@ class SignalTestCase(FHDLTestCase):
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s2 = Signal(name="sig")
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self.assertEqual(s2.name, "sig")
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def test_reset(self):
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s1 = Signal(4, reset=0b111, reset_less=True)
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self.assertEqual(s1.reset, 0b111)
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def test_init(self):
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s1 = Signal(4, init=0b111, reset_less=True)
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self.assertEqual(s1.init, 0b111)
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self.assertEqual(s1.reset_less, True)
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s2 = Signal.like(s1, init=0b011)
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self.assertEqual(s2.init, 0b011)
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def test_reset_enum(self):
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s1 = Signal(2, reset=UnsignedEnum.BAR)
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self.assertEqual(s1.reset, 2)
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def test_init_enum(self):
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s1 = Signal(2, init=UnsignedEnum.BAR)
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self.assertEqual(s1.init, 2)
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with self.assertRaisesRegex(TypeError,
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r"^Reset value must be a constant-castable expression, "
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r"^Initial value must be a constant-castable expression, "
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r"not <StringEnum\.FOO: 'a'>$"):
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Signal(1, reset=StringEnum.FOO)
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Signal(1, init=StringEnum.FOO)
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def test_reset_const_castable(self):
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s1 = Signal(4, reset=Cat(Const(0, 1), Const(1, 1), Const(0, 2)))
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self.assertEqual(s1.reset, 2)
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def test_init_const_castable(self):
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s1 = Signal(4, init=Cat(Const(0, 1), Const(1, 1), Const(0, 2)))
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self.assertEqual(s1.init, 2)
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def test_reset_shape_castable_const(self):
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def test_init_shape_castable_const(self):
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class CastableFromHex(ShapeCastable):
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def as_shape(self):
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return unsigned(8)
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@ -1168,54 +1170,80 @@ class SignalTestCase(FHDLTestCase):
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def const(self, init):
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return int(init, 16)
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s1 = Signal(CastableFromHex(), reset="aa")
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self.assertEqual(s1.reset, 0xaa)
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s1 = Signal(CastableFromHex(), init="aa")
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self.assertEqual(s1.init, 0xaa)
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with self.assertRaisesRegex(ValueError,
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r"^Constant returned by <.+?CastableFromHex.+?>\.const\(\) must have the shape "
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r"that it casts to, unsigned\(8\), and not unsigned\(1\)$"):
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Signal(CastableFromHex(), reset="01")
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Signal(CastableFromHex(), init="01")
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def test_reset_shape_castable_enum_wrong(self):
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def test_init_shape_castable_enum_wrong(self):
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class EnumA(AmaranthEnum, shape=1):
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X = 1
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with self.assertRaisesRegex(TypeError,
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r"^Reset value must be a constant initializer of <enum 'EnumA'>$"):
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Signal(EnumA) # implied reset=0
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r"^Initial value must be a constant initializer of <enum 'EnumA'>$"):
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Signal(EnumA) # implied init=0
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def test_reset_signed_mismatch(self):
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def test_init_signed_mismatch(self):
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with self.assertWarnsRegex(SyntaxWarning,
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r"^Reset value -2 is signed, but the signal shape is unsigned\(2\)$"):
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Signal(unsigned(2), reset=-2)
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r"^Initial value -2 is signed, but the signal shape is unsigned\(2\)$"):
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Signal(unsigned(2), init=-2)
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def test_reset_wrong_too_wide(self):
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def test_init_wrong_too_wide(self):
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with self.assertWarnsRegex(SyntaxWarning,
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r"^Reset value 2 will be truncated to the signal shape unsigned\(1\)$"):
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Signal(unsigned(1), reset=2)
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r"^Initial value 2 will be truncated to the signal shape unsigned\(1\)$"):
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Signal(unsigned(1), init=2)
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with self.assertWarnsRegex(SyntaxWarning,
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r"^Reset value 1 will be truncated to the signal shape signed\(1\)$"):
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Signal(signed(1), reset=1)
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r"^Initial value 1 will be truncated to the signal shape signed\(1\)$"):
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Signal(signed(1), init=1)
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with self.assertWarnsRegex(SyntaxWarning,
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r"^Reset value -2 will be truncated to the signal shape signed\(1\)$"):
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Signal(signed(1), reset=-2)
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r"^Initial value -2 will be truncated to the signal shape signed\(1\)$"):
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Signal(signed(1), init=-2)
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def test_reset_wrong_fencepost(self):
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def test_init_wrong_fencepost(self):
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with self.assertRaisesRegex(SyntaxError,
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r"^Reset value 10 equals the non-inclusive end of the signal shape "
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r"^Initial value 10 equals the non-inclusive end of the signal shape "
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r"range\(0, 10\); this is likely an off-by-one error$"):
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Signal(range(0, 10), reset=10)
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Signal(range(0, 10), init=10)
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with self.assertRaisesRegex(SyntaxError,
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r"^Reset value 0 equals the non-inclusive end of the signal shape "
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r"^Initial value 0 equals the non-inclusive end of the signal shape "
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r"range\(0, 0\); this is likely an off-by-one error$"):
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Signal(range(0), reset=0)
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Signal(range(0), init=0)
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def test_reset_wrong_range(self):
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def test_init_wrong_range(self):
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with self.assertRaisesRegex(SyntaxError,
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r"^Reset value 11 is not within the signal shape range\(0, 10\)$"):
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Signal(range(0, 10), reset=11)
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r"^Initial value 11 is not within the signal shape range\(0, 10\)$"):
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Signal(range(0, 10), init=11)
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with self.assertRaisesRegex(SyntaxError,
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r"^Reset value 0 is not within the signal shape range\(1, 10\)$"):
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Signal(range(1, 10), reset=0)
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r"^Initial value 0 is not within the signal shape range\(1, 10\)$"):
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Signal(range(1, 10), init=0)
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def test_reset(self):
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with self.assertWarnsRegex(DeprecationWarning,
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r"^`reset=` is deprecated, use `init=` instead$"):
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s1 = Signal(4, reset=0b111)
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self.assertEqual(s1.init, 0b111)
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with self.assertWarnsRegex(DeprecationWarning,
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r"^`Signal.reset` is deprecated, use `Signal.init` instead$"):
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self.assertEqual(s1.reset, 0b111)
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with self.assertWarnsRegex(DeprecationWarning,
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r"^`Signal.reset` is deprecated, use `Signal.init` instead$"):
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s1.reset = 0b010
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self.assertEqual(s1.init, 0b010)
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with self.assertWarnsRegex(DeprecationWarning,
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r"^`reset=` is deprecated, use `init=` instead$"):
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s2 = Signal.like(s1, reset=3)
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self.assertEqual(s2.init, 3)
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def test_reset_wrong(self):
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with self.assertRaisesRegex(ValueError,
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r"^Cannot specify both `reset` and `init`$"):
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Signal(4, reset=1, init=1)
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s1 = Signal(4)
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with self.assertRaisesRegex(ValueError,
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r"^Cannot specify both `reset` and `init`$"):
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Signal.like(s1, reset=1, init=1)
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def test_attrs(self):
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s1 = Signal()
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@ -1232,8 +1260,8 @@ class SignalTestCase(FHDLTestCase):
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self.assertEqual(s1.shape(), unsigned(4))
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s2 = Signal.like(Signal(range(-15, 1)))
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self.assertEqual(s2.shape(), signed(5))
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s3 = Signal.like(Signal(4, reset=0b111, reset_less=True))
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self.assertEqual(s3.reset, 0b111)
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s3 = Signal.like(Signal(4, init=0b111, reset_less=True))
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self.assertEqual(s3.init, 0b111)
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self.assertEqual(s3.reset_less, True)
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s4 = Signal.like(Signal(attrs={"no_retiming": True}))
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self.assertEqual(s4.attrs, {"no_retiming": True})
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@ -451,7 +451,7 @@ class DSLTestCase(FHDLTestCase):
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RED = 1
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BLUE = 2
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m = Module()
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se = Signal(Color, reset=Color.RED)
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se = Signal(Color, init=Color.RED)
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with m.Switch(se):
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with m.Case(Color.RED):
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m.d.comb += self.c1.eq(1)
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@ -638,10 +638,10 @@ class DSLTestCase(FHDLTestCase):
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1: "SECOND"
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}))
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def test_FSM_reset(self):
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def test_FSM_init(self):
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a = Signal()
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m = Module()
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with m.FSM(reset="SECOND"):
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with m.FSM(init="SECOND"):
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with m.State("FIRST"):
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m.d.comb += a.eq(0)
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m.next = "SECOND"
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@ -670,6 +670,55 @@ class DSLTestCase(FHDLTestCase):
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)
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)
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""")
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self.assertEqual(m._generated["fsm"].state.init, 1)
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def test_FSM_reset(self):
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a = Signal()
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m = Module()
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with self.assertWarnsRegex(DeprecationWarning,
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r"^`reset=` is deprecated, use `init=` instead$"):
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with m.FSM(reset="SECOND"):
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with m.State("FIRST"):
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m.d.comb += a.eq(0)
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m.next = "SECOND"
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with m.State("SECOND"):
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m.next = "FIRST"
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m._flush()
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self.assertRepr(m._statements["comb"], """
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(
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(switch (sig fsm_state)
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(case 0
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(eq (sig a) (const 1'd0))
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)
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(case 1 )
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)
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)
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""")
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self.assertRepr(m._statements["sync"], """
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(
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(switch (sig fsm_state)
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(case 0
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(eq (sig fsm_state) (const 1'd1))
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)
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(case 1
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(eq (sig fsm_state) (const 1'd0))
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)
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)
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)
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""")
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self.assertEqual(m._generated["fsm"].state.init, 1)
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def test_FSM_reset_wrong(self):
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a = Signal()
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m = Module()
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with self.assertRaisesRegex(ValueError,
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r"^Cannot specify both `reset` and `init`$"):
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with m.FSM(reset="SECOND", init="SECOND"):
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with m.State("FIRST"):
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m.d.comb += a.eq(0)
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m.next = "SECOND"
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with m.State("SECOND"):
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m.next = "FIRST"
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def test_FSM_ongoing(self):
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a = Signal()
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@ -683,7 +732,7 @@ class DSLTestCase(FHDLTestCase):
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with m.State("SECOND"):
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pass
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m._flush()
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self.assertEqual(m._generated["fsm"].state.reset, 1)
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self.assertEqual(m._generated["fsm"].state.init, 1)
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self.maxDiff = 10000
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self.assertRepr(m._statements["comb"], """
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(
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@ -59,7 +59,7 @@ class MemoryTestCase(FHDLTestCase):
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self.assertEqual(len(rdport.data), 8)
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self.assertEqual(len(rdport.en), 1)
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self.assertIsInstance(rdport.en, Signal)
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self.assertEqual(rdport.en.reset, 1)
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self.assertEqual(rdport.en.init, 1)
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def test_read_port_non_transparent(self):
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mem = Memory(width=8, depth=4)
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@ -69,7 +69,7 @@ class MemoryTestCase(FHDLTestCase):
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self.assertEqual(rdport.transparent, False)
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self.assertEqual(len(rdport.en), 1)
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self.assertIsInstance(rdport.en, Signal)
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self.assertEqual(rdport.en.reset, 1)
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self.assertEqual(rdport.en.init, 1)
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def test_read_port_asynchronous(self):
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mem = Memory(width=8, depth=4)
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@ -199,11 +199,11 @@ class RecordTestCase(FHDLTestCase):
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self.assertEqual(r1.a.name, "r1__a")
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self.assertEqual(r1.b.name, "r1__b")
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self.assertEqual(r1.b.s.name, "r1__b__s")
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r1.a.reset = 1
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r1.b.s.reset = 1
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r1.a.init = 1
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r1.b.s.init = 1
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r2 = Record.like(r1)
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self.assertEqual(r2.a.reset, 1)
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self.assertEqual(r2.b.s.reset, 1)
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self.assertEqual(r2.a.init, 1)
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self.assertEqual(r2.b.s.init, 1)
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self.assertEqual(r2.a.name, "r2__a")
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self.assertEqual(r2.b.name, "r2__b")
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self.assertEqual(r2.b.s.name, "r2__b__s")
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@ -247,8 +247,8 @@ class DomainLowererTestCase(FHDLTestCase):
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class ResetInserterTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal(reset=1)
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self.s3 = Signal(reset=1, reset_less=True)
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self.s2 = Signal(init=1)
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self.s3 = Signal(init=1, reset_less=True)
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self.c1 = Signal()
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def test_reset_default(self):
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@ -35,10 +35,10 @@ class FFSynchronizerTestCase(FHDLTestCase):
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sim.add_process(process)
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sim.run()
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def test_reset_value(self):
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i = Signal(reset=1)
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def test_init_value(self):
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i = Signal(init=1)
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o = Signal()
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frag = FFSynchronizer(i, o, reset=1)
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frag = FFSynchronizer(i, o, init=1)
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sim = Simulator(frag)
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sim.add_clock(1e-6)
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@ -54,6 +54,34 @@ class FFSynchronizerTestCase(FHDLTestCase):
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sim.add_process(process)
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sim.run()
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def test_reset_value(self):
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i = Signal(init=1)
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o = Signal()
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with self.assertWarnsRegex(DeprecationWarning,
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r"^`reset=` is deprecated, use `init=` instead$"):
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frag = FFSynchronizer(i, o, reset=1)
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sim = Simulator(frag)
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sim.add_clock(1e-6)
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def process():
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self.assertEqual((yield o), 1)
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yield i.eq(0)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick()
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self.assertEqual((yield o), 0)
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sim.add_process(process)
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sim.run()
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def test_reset_wrong(self):
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i = Signal(init=1)
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o = Signal()
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with self.assertRaisesRegex(ValueError,
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r"^Cannot specify both `reset` and `init`$"):
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FFSynchronizer(i, o, reset=1, init=1)
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class AsyncFFSynchronizerTestCase(FHDLTestCase):
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def test_stages_wrong(self):
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@ -115,7 +143,7 @@ class AsyncFFSynchronizerTestCase(FHDLTestCase):
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sim.run()
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def test_neg_edge(self):
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i = Signal(reset=1)
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i = Signal(init=1)
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o = Signal()
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m = Module()
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m.domains += ClockDomain("sync")
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@ -166,7 +194,7 @@ class ResetSynchronizerTestCase(FHDLTestCase):
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m = Module()
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m.domains += ClockDomain("sync")
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m.submodules += ResetSynchronizer(arst)
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s = Signal(reset=1)
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s = Signal(init=1)
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m.d.sync += s.eq(0)
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sim = Simulator(m)
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@ -430,13 +430,13 @@ class LayoutTestCase(FHDLTestCase):
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sl = StructLayout({"f": unsigned(1)})
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self.assertRepr(sl.const({"f": Const(1)}).as_value(), "(const 1'd1)")
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def test_signal_reset(self):
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def test_signal_init(self):
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sl = StructLayout({
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"a": unsigned(1),
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"b": unsigned(2)
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})
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self.assertEqual(Signal(sl).as_value().reset, 0)
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self.assertEqual(Signal(sl, reset={"a": 0b1, "b": 0b10}).as_value().reset, 5)
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self.assertEqual(Signal(sl).as_value().init, 0)
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self.assertEqual(Signal(sl, init={"a": 0b1, "b": 0b10}).as_value().init, 5)
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class ViewTestCase(FHDLTestCase):
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@ -454,17 +454,17 @@ class ViewTestCase(FHDLTestCase):
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self.assertEqual(cv.shape(), unsigned(3))
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self.assertEqual(cv.name, "v")
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def test_construct_signal_reset(self):
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def test_construct_signal_init(self):
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v1 = Signal(StructLayout({"a": unsigned(1), "b": unsigned(2)}),
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reset={"a": 0b1, "b": 0b10})
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self.assertEqual(Value.cast(v1).reset, 0b101)
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init={"a": 0b1, "b": 0b10})
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self.assertEqual(Value.cast(v1).init, 0b101)
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v2 = Signal(StructLayout({"a": unsigned(1),
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"b": StructLayout({"x": unsigned(1), "y": unsigned(1)})}),
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reset={"a": 0b1, "b": {"x": 0b0, "y": 0b1}})
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self.assertEqual(Value.cast(v2).reset, 0b101)
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init={"a": 0b1, "b": {"x": 0b0, "y": 0b1}})
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self.assertEqual(Value.cast(v2).init, 0b101)
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v3 = Signal(ArrayLayout(unsigned(2), 2),
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reset=[0b01, 0b10])
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self.assertEqual(Value.cast(v3).reset, 0b1001)
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init=[0b01, 0b10])
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self.assertEqual(Value.cast(v3).init, 0b1001)
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def test_layout_wrong(self):
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with self.assertRaisesRegex(TypeError,
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@ -625,13 +625,13 @@ class ViewTestCase(FHDLTestCase):
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def test_bug_837_array_layout_getitem_str(self):
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||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Views with array layout may only be indexed with an integer or a value, "
|
||||
r"not 'reset'$"):
|
||||
Signal(ArrayLayout(unsigned(1), 1), reset=[0])["reset"]
|
||||
r"not 'init'$"):
|
||||
Signal(ArrayLayout(unsigned(1), 1), init=[0])["init"]
|
||||
|
||||
def test_bug_837_array_layout_getattr(self):
|
||||
with self.assertRaisesRegex(AttributeError,
|
||||
r"^View of \(sig \$signal\) with an array layout does not have fields$"):
|
||||
Signal(ArrayLayout(unsigned(1), 1), reset=[0]).reset
|
||||
Signal(ArrayLayout(unsigned(1), 1), init=[0]).init
|
||||
|
||||
def test_eq(self):
|
||||
s1 = Signal(StructLayout({"a": unsigned(2)}))
|
||||
|
|
@ -735,7 +735,7 @@ class StructTestCase(FHDLTestCase):
|
|||
self.assertRepr(v.b.q.r, "(s (slice (slice (slice (sig v) 1:9) 4:8) 0:2))")
|
||||
self.assertRepr(v.b.q.s, "(s (slice (slice (slice (sig v) 1:9) 4:8) 2:4))")
|
||||
|
||||
def test_construct_reset(self):
|
||||
def test_construct_init(self):
|
||||
class S(Struct):
|
||||
p: 4
|
||||
q: 2 = 1
|
||||
|
|
@ -744,11 +744,11 @@ class StructTestCase(FHDLTestCase):
|
|||
S.q
|
||||
|
||||
v1 = Signal(S)
|
||||
self.assertEqual(v1.as_value().reset, 0b010000)
|
||||
v2 = Signal(S, reset=dict(p=0b0011))
|
||||
self.assertEqual(v2.as_value().reset, 0b010011)
|
||||
v3 = Signal(S, reset=dict(p=0b0011, q=0b00))
|
||||
self.assertEqual(v3.as_value().reset, 0b000011)
|
||||
self.assertEqual(v1.as_value().init, 0b010000)
|
||||
v2 = Signal(S, init=dict(p=0b0011))
|
||||
self.assertEqual(v2.as_value().init, 0b010011)
|
||||
v3 = Signal(S, init=dict(p=0b0011, q=0b00))
|
||||
self.assertEqual(v3.as_value().init, 0b000011)
|
||||
|
||||
def test_shape_undefined_wrong(self):
|
||||
class S(Struct):
|
||||
|
|
@ -835,33 +835,33 @@ class UnionTestCase(FHDLTestCase):
|
|||
self.assertRepr(v.a, "(slice (sig v) 0:1)")
|
||||
self.assertRepr(v.b, "(s (slice (sig v) 0:3))")
|
||||
|
||||
def test_define_reset_two_wrong(self):
|
||||
def test_define_init_two_wrong(self):
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Reset value for at most one field can be provided for a union class "
|
||||
r"^Initial value for at most one field can be provided for a union class "
|
||||
r"\(specified: a, b\)$"):
|
||||
class U(Union):
|
||||
a: unsigned(1) = 1
|
||||
b: unsigned(2) = 1
|
||||
|
||||
def test_construct_reset_two_wrong(self):
|
||||
def test_construct_init_two_wrong(self):
|
||||
class U(Union):
|
||||
a: unsigned(1)
|
||||
b: unsigned(2)
|
||||
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Reset value must be a constant initializer of <class '.+?\.U'>$") as cm:
|
||||
Signal(U, reset=dict(a=1, b=2))
|
||||
r"^Initial value must be a constant initializer of <class '.+?\.U'>$") as cm:
|
||||
Signal(U, init=dict(a=1, b=2))
|
||||
self.assertRegex(cm.exception.__cause__.message,
|
||||
r"^Initializer for at most one field can be provided for a union "
|
||||
r"class \(specified: a, b\)$")
|
||||
|
||||
def test_construct_reset_override(self):
|
||||
def test_construct_init_override(self):
|
||||
class U(Union):
|
||||
a: unsigned(1) = 1
|
||||
b: unsigned(2)
|
||||
|
||||
self.assertEqual(Signal(U).as_value().reset, 0b01)
|
||||
self.assertEqual(Signal(U, reset=dict(b=0b10)).as_value().reset, 0b10)
|
||||
self.assertEqual(Signal(U).as_value().init, 0b01)
|
||||
self.assertEqual(Signal(U, init=dict(b=0b10)).as_value().init, 0b10)
|
||||
|
||||
|
||||
# Examples from https://github.com/amaranth-lang/amaranth/issues/693
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ class MemberTestCase(unittest.TestCase):
|
|||
self.assertEqual(member.flow, In)
|
||||
self.assertEqual(member.is_port, True)
|
||||
self.assertEqual(member.shape, unsigned(1))
|
||||
self.assertEqual(member.reset, None)
|
||||
self.assertEqual(member.init, None)
|
||||
self.assertEqual(member.is_signature, False)
|
||||
with self.assertRaisesRegex(AttributeError,
|
||||
r"^A port member does not have a signature$"):
|
||||
|
|
@ -50,33 +50,58 @@ class MemberTestCase(unittest.TestCase):
|
|||
r"not 'whatever'$"):
|
||||
Member(In, "whatever")
|
||||
|
||||
def test_port_member_reset(self):
|
||||
member = Member(Out, unsigned(1), reset=1)
|
||||
def test_port_member_init(self):
|
||||
member = Member(Out, unsigned(1), init=1)
|
||||
self.assertEqual(member.flow, Out)
|
||||
self.assertEqual(member.shape, unsigned(1))
|
||||
self.assertEqual(member.reset, 1)
|
||||
self.assertEqual(repr(member._reset_as_const), repr(Const(1, 1)))
|
||||
self.assertEqual(repr(member), "Out(unsigned(1), reset=1)")
|
||||
self.assertEqual(member.init, 1)
|
||||
self.assertEqual(repr(member._init_as_const), repr(Const(1, 1)))
|
||||
self.assertEqual(repr(member), "Out(unsigned(1), init=1)")
|
||||
|
||||
def test_port_member_reset_wrong(self):
|
||||
def test_port_member_init_wrong(self):
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Port member reset value 'no' is not a valid constant initializer "
|
||||
r"^Port member initial value 'no' is not a valid constant initializer "
|
||||
r"for unsigned\(1\)$"):
|
||||
Member(In, 1, reset="no")
|
||||
Member(In, 1, init="no")
|
||||
|
||||
def test_port_member_reset_shape_castable(self):
|
||||
def test_port_member_init_shape_castable(self):
|
||||
layout = data.StructLayout({"a": 32})
|
||||
member = Member(In, layout, reset={"a": 1})
|
||||
member = Member(In, layout, init={"a": 1})
|
||||
self.assertEqual(member.flow, In)
|
||||
self.assertEqual(member.shape, layout)
|
||||
self.assertEqual(member.reset, {"a": 1})
|
||||
self.assertEqual(repr(member), "In(StructLayout({'a': 32}), reset={'a': 1})")
|
||||
self.assertEqual(member.init, {"a": 1})
|
||||
self.assertEqual(repr(member), "In(StructLayout({'a': 32}), init={'a': 1})")
|
||||
|
||||
def test_port_member_reset_shape_castable_wrong(self):
|
||||
def test_port_member_init_shape_castable_wrong(self):
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Port member reset value 'no' is not a valid constant initializer "
|
||||
r"^Port member initial value 'no' is not a valid constant initializer "
|
||||
r"for StructLayout\({'a': 32}\)$"):
|
||||
Member(In, data.StructLayout({"a": 32}), reset="no")
|
||||
Member(In, data.StructLayout({"a": 32}), init="no")
|
||||
|
||||
def test_port_member_reset(self):
|
||||
with self.assertWarnsRegex(DeprecationWarning,
|
||||
r"^`reset=` is deprecated, use `init=` instead$"):
|
||||
member = Member(Out, unsigned(1), reset=1)
|
||||
self.assertEqual(member.flow, Out)
|
||||
self.assertEqual(member.shape, unsigned(1))
|
||||
self.assertEqual(member.init, 1)
|
||||
self.assertEqual(repr(member._init_as_const), repr(Const(1, 1)))
|
||||
self.assertEqual(repr(member), "Out(unsigned(1), init=1)")
|
||||
with self.assertWarnsRegex(DeprecationWarning,
|
||||
r"^`Member.reset` is deprecated, use `Member.init` instead$"):
|
||||
self.assertEqual(member.reset, 1)
|
||||
with self.assertWarnsRegex(DeprecationWarning,
|
||||
r"^`reset=` is deprecated, use `init=` instead$"):
|
||||
member = Out(unsigned(1), reset=1)
|
||||
self.assertEqual(member.init,1)
|
||||
|
||||
def test_port_member_reset_wrong(self):
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Cannot specify both `reset` and `init`$"):
|
||||
Member(Out, unsigned(1), reset=1, init=1)
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Cannot specify both `reset` and `init`$"):
|
||||
Out(unsigned(1), reset=1, init=1)
|
||||
|
||||
def test_signature_member_out(self):
|
||||
sig = Signature({"data": Out(unsigned(32))})
|
||||
|
|
@ -87,8 +112,8 @@ class MemberTestCase(unittest.TestCase):
|
|||
r"^A signature member does not have a shape$"):
|
||||
member.shape
|
||||
with self.assertRaisesRegex(AttributeError,
|
||||
r"^A signature member does not have a reset value$"):
|
||||
member.reset
|
||||
r"^A signature member does not have an initial value$"):
|
||||
member.init
|
||||
self.assertEqual(member.is_signature, True)
|
||||
self.assertEqual(member.signature, sig)
|
||||
self.assertEqual(member.dimensions, ())
|
||||
|
|
@ -103,8 +128,8 @@ class MemberTestCase(unittest.TestCase):
|
|||
r"^A signature member does not have a shape$"):
|
||||
member.shape
|
||||
with self.assertRaisesRegex(AttributeError,
|
||||
r"^A signature member does not have a reset value$"):
|
||||
member.reset
|
||||
r"^A signature member does not have an initial value$"):
|
||||
member.init
|
||||
self.assertEqual(member.is_signature, True)
|
||||
self.assertEqual(member.signature, sig.flip())
|
||||
self.assertEqual(member.dimensions, ())
|
||||
|
|
@ -112,8 +137,8 @@ class MemberTestCase(unittest.TestCase):
|
|||
|
||||
def test_signature_member_wrong(self):
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^A signature member cannot have a reset value$"):
|
||||
Member(In, Signature({}), reset=1)
|
||||
r"^A signature member cannot have an initial value$"):
|
||||
Member(In, Signature({}), init=1)
|
||||
|
||||
def test_array(self):
|
||||
array_2 = Member(In, unsigned(1)).array(2)
|
||||
|
|
@ -143,8 +168,8 @@ class MemberTestCase(unittest.TestCase):
|
|||
def test_equality(self):
|
||||
self.assertEqual(In(1), In(1))
|
||||
self.assertNotEqual(In(1), Out(1))
|
||||
self.assertNotEqual(In(1), In(1, reset=1))
|
||||
self.assertNotEqual(In(1), In(1, reset=0))
|
||||
self.assertNotEqual(In(1), In(1, init=1))
|
||||
self.assertNotEqual(In(1), In(1, init=0))
|
||||
self.assertEqual(In(1), In(1).array())
|
||||
self.assertNotEqual(In(1), In(1).array(1))
|
||||
sig = Signature({})
|
||||
|
|
@ -237,12 +262,12 @@ class SignatureMembersTestCase(unittest.TestCase):
|
|||
self.assertEqual(attrs["s"].b.shape(), unsigned(2))
|
||||
self.assertEqual(attrs["s"].b.name, "attrs__s__b")
|
||||
|
||||
def test_create_reset(self):
|
||||
def test_create_init(self):
|
||||
members = SignatureMembers({
|
||||
"a": In(1, reset=1),
|
||||
"a": In(1, init=1),
|
||||
})
|
||||
attrs = members.create()
|
||||
self.assertEqual(attrs["a"].reset, 1)
|
||||
self.assertEqual(attrs["a"].init, 1)
|
||||
|
||||
def test_create_tuple(self):
|
||||
sig = SignatureMembers({
|
||||
|
|
@ -421,12 +446,12 @@ class SignatureTestCase(unittest.TestCase):
|
|||
sig=Signature({"a": In(unsigned(1))}),
|
||||
obj=NS(a=Signal(signed(1))))
|
||||
self.assertNotCompliant(
|
||||
r"^'obj\.a' is expected to have the reset value None, but it has the reset value 1$",
|
||||
r"^'obj\.a' is expected to have the initial value None, but it has the initial value 1$",
|
||||
sig=Signature({"a": In(1)}),
|
||||
obj=NS(a=Signal(reset=1)))
|
||||
obj=NS(a=Signal(init=1)))
|
||||
self.assertNotCompliant(
|
||||
r"^'obj\.a' is expected to have the reset value 1, but it has the reset value 0$",
|
||||
sig=Signature({"a": In(1, reset=1)}),
|
||||
r"^'obj\.a' is expected to have the initial value 1, but it has the initial value 0$",
|
||||
sig=Signature({"a": In(1, init=1)}),
|
||||
obj=NS(a=Signal(1)))
|
||||
self.assertNotCompliant(
|
||||
r"^'obj\.a' is expected to not be reset-less$",
|
||||
|
|
@ -820,21 +845,21 @@ class ConnectTestCase(unittest.TestCase):
|
|||
q=NS(signature=Signature({"a": In(Cycle)}),
|
||||
a=Signal(Cycle)))
|
||||
|
||||
def test_reset_mismatch(self):
|
||||
def test_init_mismatch(self):
|
||||
m = Module()
|
||||
with self.assertRaisesRegex(ConnectionError,
|
||||
r"^Cannot connect together the member 'q\.a' with reset value 1 and the member "
|
||||
r"'p\.a' with reset value 0 because the reset values do not match$"):
|
||||
r"^Cannot connect together the member 'q\.a' with initial value 1 and the member "
|
||||
r"'p\.a' with initial value 0 because the initial values do not match$"):
|
||||
connect(m,
|
||||
p=NS(signature=Signature({"a": Out(1, reset=0)}),
|
||||
p=NS(signature=Signature({"a": Out(1, init=0)}),
|
||||
a=Signal()),
|
||||
q=NS(signature=Signature({"a": In(1, reset=1)}),
|
||||
a=Signal(reset=1)))
|
||||
q=NS(signature=Signature({"a": In(1, init=1)}),
|
||||
a=Signal(init=1)))
|
||||
|
||||
def test_reset_none_match(self):
|
||||
def test_init_none_match(self):
|
||||
m = Module()
|
||||
connect(m,
|
||||
p=NS(signature=Signature({"a": Out(1, reset=0)}),
|
||||
p=NS(signature=Signature({"a": Out(1, init=0)}),
|
||||
a=Signal()),
|
||||
q=NS(signature=Signature({"a": In(1)}),
|
||||
a=Signal()))
|
||||
|
|
|
|||
|
|
@ -18,12 +18,12 @@ from amaranth._utils import _ignore_deprecated
|
|||
|
||||
|
||||
class SimulatorUnitTestCase(FHDLTestCase):
|
||||
def assertStatement(self, stmt, inputs, output, reset=0):
|
||||
def assertStatement(self, stmt, inputs, output, init=0):
|
||||
inputs = [Value.cast(i) for i in inputs]
|
||||
output = Value.cast(output)
|
||||
|
||||
isigs = [Signal(i.shape(), name=n) for i, n in zip(inputs, "abcd")]
|
||||
osig = Signal(output.shape(), name="y", reset=reset)
|
||||
osig = Signal(output.shape(), name="y", init=init)
|
||||
|
||||
stmt = stmt(osig, *isigs)
|
||||
frag = Fragment()
|
||||
|
|
@ -243,9 +243,9 @@ class SimulatorUnitTestCase(FHDLTestCase):
|
|||
|
||||
def test_slice_lhs(self):
|
||||
stmt1 = lambda y, a: y[2].eq(a)
|
||||
self.assertStatement(stmt1, [C(0b0, 1)], C(0b11111011, 8), reset=0b11111111)
|
||||
self.assertStatement(stmt1, [C(0b0, 1)], C(0b11111011, 8), init=0b11111111)
|
||||
stmt2 = lambda y, a: y[2:4].eq(a)
|
||||
self.assertStatement(stmt2, [C(0b01, 2)], C(0b11110111, 8), reset=0b11111011)
|
||||
self.assertStatement(stmt2, [C(0b01, 2)], C(0b11110111, 8), init=0b11111011)
|
||||
|
||||
def test_bit_select(self):
|
||||
stmt = lambda y, a, b: y.eq(a.bit_select(b, 3))
|
||||
|
|
@ -255,9 +255,9 @@ class SimulatorUnitTestCase(FHDLTestCase):
|
|||
|
||||
def test_bit_select_lhs(self):
|
||||
stmt = lambda y, a, b: y.bit_select(a, 3).eq(b)
|
||||
self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), reset=0b11111111)
|
||||
self.assertStatement(stmt, [C(2), C(0b101, 3)], C(0b11110111, 8), reset=0b11111111)
|
||||
self.assertStatement(stmt, [C(3), C(0b110, 3)], C(0b11110111, 8), reset=0b11111111)
|
||||
self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), init=0b11111111)
|
||||
self.assertStatement(stmt, [C(2), C(0b101, 3)], C(0b11110111, 8), init=0b11111111)
|
||||
self.assertStatement(stmt, [C(3), C(0b110, 3)], C(0b11110111, 8), init=0b11111111)
|
||||
|
||||
def test_word_select(self):
|
||||
stmt = lambda y, a, b: y.eq(a.word_select(b, 3))
|
||||
|
|
@ -267,9 +267,9 @@ class SimulatorUnitTestCase(FHDLTestCase):
|
|||
|
||||
def test_word_select_lhs(self):
|
||||
stmt = lambda y, a, b: y.word_select(a, 3).eq(b)
|
||||
self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), reset=0b11111111)
|
||||
self.assertStatement(stmt, [C(1), C(0b101, 3)], C(0b11101111, 8), reset=0b11111111)
|
||||
self.assertStatement(stmt, [C(2), C(0b110, 3)], C(0b10111111, 8), reset=0b11111111)
|
||||
self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), init=0b11111111)
|
||||
self.assertStatement(stmt, [C(1), C(0b101, 3)], C(0b11101111, 8), init=0b11111111)
|
||||
self.assertStatement(stmt, [C(2), C(0b110, 3)], C(0b10111111, 8), init=0b11111111)
|
||||
|
||||
def test_cat(self):
|
||||
stmt = lambda y, *xs: y.eq(Cat(*xs))
|
||||
|
|
@ -315,9 +315,9 @@ class SimulatorUnitTestCase(FHDLTestCase):
|
|||
self.assertStatement(stmt, [C(4)], C(10))
|
||||
|
||||
def test_array_lhs(self):
|
||||
l = Signal(3, reset=1)
|
||||
m = Signal(3, reset=4)
|
||||
n = Signal(3, reset=7)
|
||||
l = Signal(3, init=1)
|
||||
m = Signal(3, init=4)
|
||||
n = Signal(3, init=7)
|
||||
array = Array([l, m, n])
|
||||
stmt = lambda y, a, b: [array[a].eq(b), y.eq(Cat(*array))]
|
||||
self.assertStatement(stmt, [C(0), C(0b000)], C(0b111100000))
|
||||
|
|
@ -426,7 +426,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
sim.run_until(deadline)
|
||||
|
||||
def setUp_counter(self):
|
||||
self.count = Signal(3, reset=4)
|
||||
self.count = Signal(3, init=4)
|
||||
self.sync = ClockDomain()
|
||||
|
||||
self.m = Module()
|
||||
|
|
@ -876,7 +876,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
|
||||
def test_comb_bench_process(self):
|
||||
m = Module()
|
||||
a = Signal(reset=1)
|
||||
a = Signal(init=1)
|
||||
b = Signal()
|
||||
m.d.comb += b.eq(a)
|
||||
with self.assertSimulation(m) as sim:
|
||||
|
|
@ -890,7 +890,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
|
||||
def test_sync_bench_process(self):
|
||||
m = Module()
|
||||
a = Signal(reset=1)
|
||||
a = Signal(init=1)
|
||||
b = Signal()
|
||||
m.d.sync += b.eq(a)
|
||||
t = Signal()
|
||||
|
|
|
|||
Loading…
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Reference in a new issue