fhdl.ast.Signal: implement reset_less signals.
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1d46ffb591
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@ -492,6 +492,10 @@ class Signal(Value, DUID):
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domain is reset, the ``Signal`` assumes the given value. When this ``Signal`` is unassigned
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in combinatorial context (due to conditional assignments not being taken), the ``Signal``
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assumes its ``reset`` value. Defaults to 0.
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reset_less : bool
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If ``True``, do not generate reset logic for this ``Signal`` in synchronous statements.
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The ``reset`` value is only used as a combinatorial default or as the initial value.
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Defaults to ``False``.
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Attributes
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----------
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@ -501,7 +505,7 @@ class Signal(Value, DUID):
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reset : int
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"""
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def __init__(self, bits_sign=1, reset=0, name=None):
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def __init__(self, bits_sign=1, name=None, reset=0, reset_less=False):
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super().__init__()
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if name is None:
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@ -517,6 +521,7 @@ class Signal(Value, DUID):
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if not isinstance(self.nbits, int) or self.nbits < 0:
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raise TypeError("Width must be a positive integer")
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self.reset = reset
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self.reset_less = reset_less
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def bits_sign(self):
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return self.nbits, self.signed
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@ -114,7 +114,7 @@ class _ControlInserter:
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class ResetInserter(_ControlInserter):
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def _wrap_control(self, fragment, cd_name, signals):
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stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals]
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stmts = [s.eq(Const(s.reset, s.nbits)) for s in signals if not s.reset_less]
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fragment.add_statements(Switch(self.controls[cd_name], {1: stmts}))
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