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build.res: simplify emission of port constraints on individual bits.

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This commit is contained in:
whitequark 2019-06-04 08:37:52 +00:00
parent 9f643ce005
commit 2763b403f1
2 changed files with 13 additions and 10 deletions
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8
nmigen/build/res.py
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@ -183,6 +183,14 @@ class ConstraintManager:
else:
assert False
def iter_port_constraints_bits(self):
for port_name, pin_names, extras in self.iter_port_constraints():
if len(pin_names) == 1:
yield port_name, pin_names[0], extras
else:
for bit, pin_name in enumerate(pin_names):
yield "{}[{}]".format(port_name, bit), pin_name, extras
def iter_clock_constraints(self):
for name, number in self.clocks.keys() & self._requested.keys():
resource = self.resources[name, number]

15
nmigen/vendor/fpga/lattice_ice40.py vendored
View file

@ -24,8 +24,9 @@ class LatticeICE40Platform(TemplatedPlatform):
* ``synth_opts``: adds options for ``synth_ice40`` Yosys command.
* ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
* ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script.
* ``yosys_opts``: overrides default options (``-q``) for Yosys.
* ``nextpnr_opts``: overrides default options (``-q --placer heap``).
* ``yosys_opts``: adds extra options for Yosys.
* ``nextpnr_opts``: adds extra and overrides default options (``--placer heap``)
for nextpnr.
Build products:
* ``{{name}}.rpt``: Yosys log.
@ -61,14 +62,8 @@ class LatticeICE40Platform(TemplatedPlatform):
""",
"{{name}}.pcf": r"""
# {{autogenerated}}
{% for port, pins, extra in platform.iter_port_constraints() %}
{% if pins|count > 1 %}
{% for bit in range -%}
set_io {{port}}[{{bit}}] {{pins[bit]}}
{% endfor %}
{% else -%}
set_io {{port}} {{pins[0]}}
{% endif %}
{% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
set_io {{port_name}} {{pin_name}}
{% endfor %}
""",
"{{name}}_pre_pack.py": r"""