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build.res: simplify emission of port constraints on individual bits.

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This commit is contained in:
whitequark 2019-06-04 08:37:52 +00:00
parent 9f643ce005
commit 2763b403f1
2 changed files with 13 additions and 10 deletions
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8
nmigen/build/res.py
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@ -183,6 +183,14 @@ class ConstraintManager:
else:
assert False
def iter_port_constraints_bits(self):
for port_name, pin_names, extras in self.iter_port_constraints():
if len(pin_names) == 1:
yield port_name, pin_names[0], extras
else:
for bit, pin_name in enumerate(pin_names):
yield "{}[{}]".format(port_name, bit), pin_name, extras
def iter_clock_constraints(self):
for name, number in self.clocks.keys() & self._requested.keys():
resource = self.resources[name, number]