compat.fhdl: reexport Array.

doc/COMPAT_SUMMARY.md

@@ -77,8 +77,8 @@ Compatibility summary
       - (-) `_check_statement` **obs** → `Statement.wrap`
       - (+) `If` **obs** → `.hdl.dsl.Module.If`
       - (+) `Case` **obs** → `.hdl.dsl.Module.Switch`
-      - (−) `_ArrayProxy` ?
-      - (−) `Array` ?
+      - (+) `_ArrayProxy` → `.hdl.ast.ArrayProxy`, `choices=`→`elems=`, `key=`→`index=`
+      - (+) `Array` id
       - (+) `ClockDomain` → `.hdl.cd.ClockDomain`
       - (−) `_ClockDomainList` ?
       - (−) `SPECIAL_INPUT`/`SPECIAL_OUTPUT`/`SPECIAL_INOUT` ?

nmigen/compat/fhdl/structure.py

@@ -2,7 +2,8 @@ from collections import OrderedDict
 
 from ...tools import deprecated
 from ...hdl import ast
-from ...hdl.ast import DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal
+from ...hdl.ast import (DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal,
+                        Array, ArrayProxy as _ArrayProxy)
 from ...hdl.cd import ClockDomain
 
 
@@ -84,8 +85,4 @@ class Case(ast.Switch):
         return self
 
 
-def Array(*args):
-    raise NotImplementedError
-
-
 (SPECIAL_INPUT, SPECIAL_OUTPUT, SPECIAL_INOUT) = range(3)

nmigen/hdl/ast.py

@@ -713,7 +713,7 @@ class Array(MutableSequence):
             master.dat_r.eq(buses[sel].dat_r),
         ]
     """
-    def __init__(self, iterable):
+    def __init__(self, iterable=()):
         self._inner    = list(iterable)
         self._proxy_at = None
         self._mutable  = True