lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin.
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whitequark
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50fa2516fa
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287a0531b3
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@ -7,4 +7,4 @@ from .hdl.rec import Record
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from .hdl.xfrm import ResetInserter, CEInserter
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from .lib.cdc import MultiReg
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from .lib.io import TSTriple
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# from .lib.io import
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@ -4,38 +4,57 @@ from ...tools import deprecated, extend
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from ...hdl.ast import *
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from ...hdl.mem import Memory as NativeMemory
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from ...hdl.ir import Fragment, Instance
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from ...lib.io import TSTriple as NativeTSTriple, Tristate as NativeTristate
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from .module import Module as CompatModule
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__all__ = ["TSTriple", "Instance", "Memory", "READ_FIRST", "WRITE_FIRST", "NO_CHANGE"]
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class CompatTSTriple(NativeTSTriple):
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class TSTriple:
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def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0, reset_i=0,
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name=None):
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super().__init__(shape=bits_sign, min=min, max=max,
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reset_o=reset_o, reset_oe=reset_oe, reset_i=reset_i,
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name=name)
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self.o = Signal(shape, min=min, max=max, reset=reset_o,
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name=None if name is None else name + "_o")
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self.oe = Signal(reset=reset_oe,
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name=None if name is None else name + "_oe")
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self.i = Signal(shape, min=min, max=max, reset=reset_i,
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name=None if name is None else name + "_i")
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def __len__(self):
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return len(self.o)
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def elaborate(self, platform):
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return Fragment()
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def get_tristate(self, io):
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return Tristate(io, self.o, self.oe, self.i)
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class CompatTristate(NativeTristate):
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class Tristate:
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def __init__(self, target, o, oe, i=None):
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triple = TSTriple()
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triple.o = o
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triple.oe = oe
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self.target = target
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self.triple = TSTriple()
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self.triple.o = o
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self.triple.oe = oe
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if i is not None:
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triple.i = i
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super().__init__(triple, target)
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self.triple.i = i
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@property
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@deprecated("instead of `Tristate.target`, use `Tristate.io`")
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def target(self):
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return self.io
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def elaborate(self, platform):
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if hasattr(platform, "get_tristate"):
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return platform.get_tristate(self.triple, self.io)
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m = Module()
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m.d.comb += self.triple.i.eq(self.io)
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m.submodules += Instance("$tribuf",
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p_WIDTH=len(self.io),
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i_EN=self.triple.oe,
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i_A=self.triple.o,
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o_Y=self.io,
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)
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TSTriple = CompatTSTriple
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Tristate = CompatTristate
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f = m.elaborate(platform)
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f.flatten = True
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return f
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(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
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115
nmigen/lib/io.py
115
nmigen/lib/io.py
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@ -1,47 +1,92 @@
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from .. import *
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from ..hdl.rec import *
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__all__ = ["TSTriple", "Tristate"]
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__all__ = ["pin_layout", "Pin"]
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class TSTriple:
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def __init__(self, shape=None, min=None, max=None, reset_o=0, reset_oe=0, reset_i=0,
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name=None):
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self.o = Signal(shape, min=min, max=max, reset=reset_o,
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name=None if name is None else name + "_o")
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self.oe = Signal(reset=reset_oe,
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name=None if name is None else name + "_oe")
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self.i = Signal(shape, min=min, max=max, reset=reset_i,
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name=None if name is None else name + "_i")
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def pin_layout(width, dir, xdr=1):
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"""
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Layout of the platform interface of a pin or several pins, which may be used inside
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user-defined records.
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def __len__(self):
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return len(self.o)
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See :class:`Pin` for details.
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"""
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if not isinstance(width, int) or width < 1:
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raise TypeError("Width must be a positive integer, not '{!r}'"
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.format(width))
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if dir not in ("i", "o", "io"):
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raise TypeError("Direction must be one of \"i\", \"o\" or \"io\", not '{!r}'"""
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.format(dir))
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if not isinstance(xdr, int) or xdr < 1:
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raise TypeError("Gearing ratio must be a positive integer, not '{!r}'"
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.format(xdr))
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def elaborate(self, platform):
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return Fragment()
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def get_tristate(self, io):
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return Tristate(self, io)
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fields = []
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if dir in ("i", "io"):
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if xdr == 1:
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fields.append(("i", width))
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else:
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for n in range(xdr):
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fields.append(("i{}".format(n), width))
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if dir in ("o", "io"):
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if xdr == 1:
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fields.append(("o", width))
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else:
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for n in range(xdr):
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fields.append(("o{}".format(n), width))
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if dir == "io":
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fields.append(("oe", 1))
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return Layout(fields)
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class Tristate:
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def __init__(self, triple, io):
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self.triple = triple
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self.io = io
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class Pin(Record):
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"""
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An interface to an I/O buffer or a group of them that provides uniform access to input, output,
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or tristate buffers that may include a 1:n gearbox. (A 1:2 gearbox is typically called "DDR".)
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def elaborate(self, platform):
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if hasattr(platform, "get_tristate"):
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return platform.get_tristate(self.triple, self.io)
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A :class:`Pin` is identical to a :class:`Record` that uses the corresponding :meth:`pin_layout`
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except that it allos accessing the parameters like ``width`` as attributes. It is legal to use
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a plain :class:`Record` anywhere a :class:`Pin` is used, provided that these attributes are
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not necessary.
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m = Module()
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m.d.comb += self.triple.i.eq(self.io)
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m.submodules += Instance("$tribuf",
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p_WIDTH=len(self.io),
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i_EN=self.triple.oe,
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i_A=self.triple.o,
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o_Y=self.io,
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)
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Parameters
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----------
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width : int
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Width of the ``i``/``iN`` and ``o``/``oN`` signals.
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dir : ``"i"``, ``"o"``, ``"io"``
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Direction of the buffers. If ``"i"`` is specified, only the ``i``/``iN`` signals are
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present. If ``"o"`` is specified, only the ``o``/``oN`` signals are present. If ``"io"``
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is specified, both the ``i``/``iN`` and ``o``/``oN`` signals are present, and an ``oe``
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signal is present.
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xdr : int
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Gearbox ratio. If equal to 1, the I/O buffer is SDR, and only ``i``/``o`` signals are
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present. If greater than 1, the I/O buffer includes a gearbox, and ``iN``/``oN`` signals
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are present instead, where ``N in range(0, N)``. For example, if ``xdr=2``, the I/O buffer
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is DDR; the signal ``i0`` reflects the value at the rising edge, and the signal ``i1``
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reflects the value at the falling edge.
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f = m.elaborate(platform)
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f.flatten = True
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return f
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Attributes
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----------
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i : Signal, out
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I/O buffer input, without gearing. Present if ``dir="i"`` or ``dir="io"``, and ``xdr`` is
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equal to 1.
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i0, i1, ... : Signal, out
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I/O buffer inputs, with gearing. Present if ``dir="i"`` or ``dir="io"``, and ``xdr`` is
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greater than 1.
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o : Signal, in
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I/O buffer output, without gearing. Present if ``dir="o"`` or ``dir="io"``, and ``xdr`` is
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equal to 1.
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o0, o1, ... : Signal, in
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I/O buffer outputs, with gearing. Present if ``dir="o"`` or ``dir="io"``, and ``xdr`` is
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greater than 1.
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oe : Signal, in
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I/O buffer output enable. Present if ``dir="io"``. Buffers generally cannot change
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direction more than once per cycle, so at most one output enable signal is present.
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"""
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def __init__(self, width, dir, xdr=1):
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self.width = width
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self.dir = dir
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self.xdr = xdr
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super().__init__(pin_layout(self.width, self.dir, self.xdr))
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98
nmigen/test/test_lib_io.py
Normal file
98
nmigen/test/test_lib_io.py
Normal file
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@ -0,0 +1,98 @@
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from .tools import *
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from ..hdl.ast import *
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from ..hdl.rec import *
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from ..lib.io import *
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class PinLayoutSDRTestCase(FHDLTestCase):
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def test_pin_layout_i(self):
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layout_1 = pin_layout(1, dir="i")
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self.assertEqual(layout_1.fields, {
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"i": (1, DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="i")
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self.assertEqual(layout_2.fields, {
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"i": (2, DIR_NONE),
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})
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def test_pin_layout_o(self):
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layout_1 = pin_layout(1, dir="o")
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self.assertEqual(layout_1.fields, {
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"o": (1, DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="o")
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self.assertEqual(layout_2.fields, {
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"o": (2, DIR_NONE),
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})
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def test_pin_layout_io(self):
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layout_1 = pin_layout(1, dir="io")
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self.assertEqual(layout_1.fields, {
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"i": (1, DIR_NONE),
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"o": (1, DIR_NONE),
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"oe": (1, DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="io")
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self.assertEqual(layout_2.fields, {
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"i": (2, DIR_NONE),
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"o": (2, DIR_NONE),
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"oe": (1, DIR_NONE),
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})
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class PinLayoutDDRTestCase(FHDLTestCase):
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def test_pin_layout_i(self):
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layout_1 = pin_layout(1, dir="i", xdr=2)
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self.assertEqual(layout_1.fields, {
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"i0": (1, DIR_NONE),
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"i1": (1, DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="i", xdr=2)
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self.assertEqual(layout_2.fields, {
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"i0": (2, DIR_NONE),
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"i1": (2, DIR_NONE),
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})
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def test_pin_layout_o(self):
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layout_1 = pin_layout(1, dir="o", xdr=2)
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self.assertEqual(layout_1.fields, {
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"o0": (1, DIR_NONE),
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"o1": (1, DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="o", xdr=2)
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self.assertEqual(layout_2.fields, {
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"o0": (2, DIR_NONE),
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"o1": (2, DIR_NONE),
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})
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def test_pin_layout_io(self):
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layout_1 = pin_layout(1, dir="io", xdr=2)
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self.assertEqual(layout_1.fields, {
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"i0": (1, DIR_NONE),
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"i1": (1, DIR_NONE),
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"o0": (1, DIR_NONE),
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"o1": (1, DIR_NONE),
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"oe": (1, DIR_NONE),
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})
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layout_2 = pin_layout(2, dir="io", xdr=2)
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self.assertEqual(layout_2.fields, {
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"i0": (2, DIR_NONE),
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"i1": (2, DIR_NONE),
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"o0": (2, DIR_NONE),
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"o1": (2, DIR_NONE),
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"oe": (1, DIR_NONE),
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})
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class PinTestCase(FHDLTestCase):
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def test_attributes(self):
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pin = Pin(2, dir="io", xdr=2)
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self.assertEqual(pin.width, 2)
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self.assertEqual(pin.dir, "io")
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self.assertEqual(pin.xdr, 2)
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