hdl.ir: allow ClockSignal and ResetSignal in ports.

Fixes #248.

nmigen/hdl/ir.py

@@ -540,6 +540,7 @@ class Fragment:
         if ports is None:
             fragment._propagate_ports(ports=(), all_undef_as_ports=True)
         else:
+            ports = map(DomainLowerer(fragment.domains).on_value, ports)
             new_ports = []
             for cd in new_domains:
                 new_ports.append(cd.clk)

nmigen/hdl/xfrm.py

@@ -486,8 +486,8 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer)
 
 
 class DomainLowerer(FragmentTransformer, ValueTransformer, StatementTransformer):
-    def __init__(self):
-        self.domains = None
+    def __init__(self, domains=None):
+        self.domains = domains
 
     def _resolve(self, domain, context):
         if domain not in self.domains:

nmigen/test/test_hdl_ir.py

@@ -264,6 +264,17 @@ class FragmentPortsTestCase(FHDLTestCase):
             (s, "io")
         ]))
 
+    def test_clk_rst(self):
+        sync = ClockDomain()
+        f = Fragment()
+        f.add_domains(sync)
+
+        f = f.prepare(ports=(ClockSignal("sync"), ResetSignal("sync")))
+        self.assertEqual(f.ports, SignalDict([
+            (sync.clk, "i"),
+            (sync.rst, "i"),
+        ]))
+
 
 class FragmentDomainsTestCase(FHDLTestCase):
     def test_iter_signals(self):