hdl.ir: allow ClockSignal and ResetSignal in ports.

Fixes #248.
2019-10-13 03:39:56 +00:00 · 2019-10-13 03:39:56 +00:00 · 29253295ee
commit 29253295ee
parent 722b3879f4
3 changed files with 14 additions and 2 deletions
--- a/nmigen/test/test_hdl_ir.py
+++ b/nmigen/test/test_hdl_ir.py
@ -264,6 +264,17 @@ class FragmentPortsTestCase(FHDLTestCase):
            (s, "io")
        ]))

+    def test_clk_rst(self):
+        sync = ClockDomain()
+        f = Fragment()
+        f.add_domains(sync)
+
+        f = f.prepare(ports=(ClockSignal("sync"), ResetSignal("sync")))
+        self.assertEqual(f.ports, SignalDict([
+            (sync.clk, "i"),
+            (sync.rst, "i"),
+        ]))
+

 class FragmentDomainsTestCase(FHDLTestCase):
    def test_iter_signals(self):