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hdl.ir: allow ClockSignal and ResetSignal in ports.

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Fixes #248.
This commit is contained in:
whitequark 2019-10-13 03:39:56 +00:00
parent 722b3879f4
commit 29253295ee
3 changed files with 14 additions and 2 deletions
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1
nmigen/hdl/ir.py
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@ -540,6 +540,7 @@ class Fragment:
if ports is None: if ports is None:
fragment._propagate_ports(ports=(), all_undef_as_ports=True) fragment._propagate_ports(ports=(), all_undef_as_ports=True)
else: else:
ports = map(DomainLowerer(fragment.domains).on_value, ports)
new_ports = [] new_ports = []
for cd in new_domains: for cd in new_domains:
new_ports.append(cd.clk) new_ports.append(cd.clk)

4
nmigen/hdl/xfrm.py
View file

@ -486,8 +486,8 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer)
class DomainLowerer(FragmentTransformer, ValueTransformer, StatementTransformer): class DomainLowerer(FragmentTransformer, ValueTransformer, StatementTransformer):
def __init__(self): def __init__(self, domains=None):
self.domains = None self.domains = domains
def _resolve(self, domain, context): def _resolve(self, domain, context):
if domain not in self.domains: if domain not in self.domains:

11
nmigen/test/test_hdl_ir.py
View file

@ -264,6 +264,17 @@ class FragmentPortsTestCase(FHDLTestCase):
(s, "io") (s, "io")
])) ]))
def test_clk_rst(self):
sync = ClockDomain()
f = Fragment()
f.add_domains(sync)
f = f.prepare(ports=(ClockSignal("sync"), ResetSignal("sync")))
self.assertEqual(f.ports, SignalDict([
(sync.clk, "i"),
(sync.rst, "i"),
]))
class FragmentDomainsTestCase(FHDLTestCase): class FragmentDomainsTestCase(FHDLTestCase):
def test_iter_signals(self): def test_iter_signals(self):