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vendor.xilinx_{7series,spartan6}: cleanup. NFC.

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Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
This commit is contained in:
whitequark 2019-06-15 16:01:37 +00:00
parent 8b34602d91
commit 2a8e7bc6f2
3 changed files with 44 additions and 36 deletions
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16
nmigen/vendor/lattice_ice40.py vendored
View file

@ -129,7 +129,7 @@ class LatticeICE40Platform(TemplatedPlatform):
i_D=d, i_D=d,
o_Q=q) o_Q=q)
def get_i_inverter(y, invert): def get_ixor(y, invert):
if invert is None: if invert is None:
return y return y
else: else:
@ -144,7 +144,7 @@ class LatticeICE40Platform(TemplatedPlatform):
o_O=y[bit]) o_O=y[bit])
return a return a
def get_o_inverter(a, invert): def get_oxor(a, invert):
if invert is None: if invert is None:
return a return a
else: else:
@ -168,16 +168,16 @@ class LatticeICE40Platform(TemplatedPlatform):
if "i" in pin.dir: if "i" in pin.dir:
if pin.xdr < 2: if pin.xdr < 2:
pin_i = get_i_inverter(pin.i, i_invert) pin_i = get_ixor(pin.i, i_invert)
elif pin.xdr == 2: elif pin.xdr == 2:
pin_i0 = get_i_inverter(pin.i0, i_invert) pin_i0 = get_ixor(pin.i0, i_invert)
pin_i1 = get_i_inverter(pin.i1, i_invert) pin_i1 = get_ixor(pin.i1, i_invert)
if "o" in pin.dir: if "o" in pin.dir:
if pin.xdr < 2: if pin.xdr < 2:
pin_o = get_o_inverter(pin.o, o_invert) pin_o = get_oxor(pin.o, o_invert)
elif pin.xdr == 2: elif pin.xdr == 2:
pin_o0 = get_o_inverter(pin.o0, o_invert) pin_o0 = get_oxor(pin.o0, o_invert)
pin_o1 = get_o_inverter(pin.o1, o_invert) pin_o1 = get_oxor(pin.o1, o_invert)
if "i" in pin.dir and pin.xdr == 2: if "i" in pin.dir and pin.xdr == 2:
i0_ff = Signal.like(pin_i0, name_suffix="_ff") i0_ff = Signal.like(pin_i0, name_suffix="_ff")

26
nmigen/vendor/xilinx_7series.py vendored
View file

@ -156,7 +156,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
o_Q=q[bit] o_Q=q[bit]
) )
def get_i_inverter(y, invert): def get_ixor(y, invert):
if invert is None: if invert is None:
return y return y
else: else:
@ -169,7 +169,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
) )
return a return a
def get_o_inverter(a, invert): def get_oxor(a, invert):
if invert is None: if invert is None:
return a return a
else: else:
@ -184,28 +184,32 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
if "i" in pin.dir: if "i" in pin.dir:
if pin.xdr < 2: if pin.xdr < 2:
pin_i = get_i_inverter(pin.i, i_invert) pin_i = get_ixor(pin.i, i_invert)
elif pin.xdr == 2: elif pin.xdr == 2:
pin_i0 = get_i_inverter(pin.i0, i_invert) pin_i0 = get_ixor(pin.i0, i_invert)
pin_i1 = get_i_inverter(pin.i1, i_invert) pin_i1 = get_ixor(pin.i1, i_invert)
if "o" in pin.dir: if "o" in pin.dir:
if pin.xdr < 2: if pin.xdr < 2:
pin_o = get_o_inverter(pin.o, o_invert) pin_o = get_oxor(pin.o, o_invert)
elif pin.xdr == 2: elif pin.xdr == 2:
pin_o0 = get_o_inverter(pin.o0, o_invert) pin_o0 = get_oxor(pin.o0, o_invert)
pin_o1 = get_o_inverter(pin.o1, o_invert) pin_o1 = get_oxor(pin.o1, o_invert)
i = o = t = None
if "i" in pin.dir:
i = Signal(pin.width, name="{}_xdr_i".format(pin.name)) i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
if "o" in pin.dir:
o = Signal(pin.width, name="{}_xdr_o".format(pin.name)) o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
if pin.dir in ("oe", "io"):
t = Signal(1, name="{}_xdr_t".format(pin.name)) t = Signal(1, name="{}_xdr_t".format(pin.name))
if pin.xdr == 0: if pin.xdr == 0:
if "i" in pin.dir: if "i" in pin.dir:
m.d.comb += pin_i.eq(i) i = pin_i
if "o" in pin.dir: if "o" in pin.dir:
m.d.comb += o.eq(pin_o) o = pin_o
if pin.dir in ("oe", "io"): if pin.dir in ("oe", "io"):
m.d.comb += t.eq(~pin.oe) t = ~pin.oe
elif pin.xdr == 1: elif pin.xdr == 1:
if "i" in pin.dir: if "i" in pin.dir:
get_dff(pin.i_clk, i, pin_i) get_dff(pin.i_clk, i, pin_i)

26
nmigen/vendor/xilinx_spartan6.py vendored
View file

@ -167,7 +167,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
o_Q=q[bit] o_Q=q[bit]
) )
def get_i_inverter(y, invert): def get_ixor(y, invert):
if invert is None: if invert is None:
return y return y
else: else:
@ -180,7 +180,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
) )
return a return a
def get_o_inverter(a, invert): def get_oxor(a, invert):
if invert is None: if invert is None:
return a return a
else: else:
@ -195,28 +195,32 @@ class XilinxSpartan6Platform(TemplatedPlatform):
if "i" in pin.dir: if "i" in pin.dir:
if pin.xdr < 2: if pin.xdr < 2:
pin_i = get_i_inverter(pin.i, i_invert) pin_i = get_ixor(pin.i, i_invert)
elif pin.xdr == 2: elif pin.xdr == 2:
pin_i0 = get_i_inverter(pin.i0, i_invert) pin_i0 = get_ixor(pin.i0, i_invert)
pin_i1 = get_i_inverter(pin.i1, i_invert) pin_i1 = get_ixor(pin.i1, i_invert)
if "o" in pin.dir: if "o" in pin.dir:
if pin.xdr < 2: if pin.xdr < 2:
pin_o = get_o_inverter(pin.o, o_invert) pin_o = get_oxor(pin.o, o_invert)
elif pin.xdr == 2: elif pin.xdr == 2:
pin_o0 = get_o_inverter(pin.o0, o_invert) pin_o0 = get_oxor(pin.o0, o_invert)
pin_o1 = get_o_inverter(pin.o1, o_invert) pin_o1 = get_oxor(pin.o1, o_invert)
i = o = t = None
if "i" in pin.dir:
i = Signal(pin.width, name="{}_xdr_i".format(pin.name)) i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
if "o" in pin.dir:
o = Signal(pin.width, name="{}_xdr_o".format(pin.name)) o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
if pin.dir in ("oe", "io"):
t = Signal(1, name="{}_xdr_t".format(pin.name)) t = Signal(1, name="{}_xdr_t".format(pin.name))
if pin.xdr == 0: if pin.xdr == 0:
if "i" in pin.dir: if "i" in pin.dir:
m.d.comb += pin_i.eq(i) i = pin_i
if "o" in pin.dir: if "o" in pin.dir:
m.d.comb += o.eq(pin_o) o = pin_o
if pin.dir in ("oe", "io"): if pin.dir in ("oe", "io"):
m.d.comb += t.eq(~pin.oe) t = ~pin.oe
elif pin.xdr == 1: elif pin.xdr == 1:
if "i" in pin.dir: if "i" in pin.dir:
get_dff(pin.i_clk, i, pin_i) get_dff(pin.i_clk, i, pin_i)