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vendor.xilinx_7series: fix typos.

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Jean-François Nguyen 2019-06-07 00:54:52 +02:00 committed by whitequark
parent 12e8fe484d
commit 2b3a0e9fa0
1 changed files with 2 additions and 2 deletions
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4
nmigen/vendor/xilinx_7series.py vendored
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@ -63,7 +63,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
add_files {{name}}.v add_files {{name}}.v
read_xdc {{name}}.xdc read_xdc {{name}}.xdc
{{get_override("script_after_read")|default("# (script_after_read placeholder)")}} {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
synth_design -top {{name}} -part {{platform.device}} synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speedgrade}}
{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}} {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
report_timing_summary -file {{name}}_timing_synth.rpt report_timing_summary -file {{name}}_timing_synth.rpt
report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
@ -100,8 +100,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
{% endfor %} {% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%} {% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_ports {{signal.name}}] create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_ports {{signal.name}}]
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
{% endfor %} {% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""" """
} }
command_templates = [ command_templates = [