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back.rtlil: fix swapped operands in mux codegen.

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This commit is contained in:
whitequark 2018-12-23 06:47:38 +00:00
parent cf79738744
commit 2b6ddbb713
1 changed files with 8 additions and 8 deletions
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16
nmigen/back/rtlil.py
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@ -429,17 +429,17 @@ class _RHSValueCompiler(_ValueCompiler):
return res return res
def on_Operator_mux(self, value): def on_Operator_mux(self, value):
sel, lhs, rhs = value.operands sel, val1, val0 = value.operands
lhs_bits, lhs_sign = lhs.shape() val1_bits, val1_sign = val1.shape()
rhs_bits, rhs_sign = rhs.shape() val0_bits, val0_sign = val0.shape()
res_bits, res_sign = value.shape() res_bits, res_sign = value.shape()
lhs_bits = rhs_bits = res_bits = max(lhs_bits, rhs_bits, res_bits) val1_bits = val0_bits = res_bits = max(val1_bits, val0_bits, res_bits)
lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign) val1_wire = self.match_shape(val1, val1_bits, val1_sign)
rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign) val0_wire = self.match_shape(val0, val0_bits, val0_sign)
res = self.s.rtlil.wire(width=res_bits) res = self.s.rtlil.wire(width=res_bits)
self.s.rtlil.cell("$mux", ports={ self.s.rtlil.cell("$mux", ports={
"\\A": lhs_wire, "\\A": val0_wire,
"\\B": rhs_wire, "\\B": val1_wire,
"\\S": self(sel), "\\S": self(sel),
"\\Y": res, "\\Y": res,
}, params={ }, params={