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README: update Yosys version requirement.

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whitequark 2019-09-12 14:33:38 +00:00
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README.md
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@ -14,7 +14,7 @@ See the [doc/](doc/) folder for more technical information.
nMigen is a direct descendant of [Migen][] rewritten from scratch to address many issues that became clear in the many years Migen has been used in production. nMigen provides an extensive compatibility layer that makes it possible to build and simulate most Migen designs unmodified, as well as integrate modules written for Migen and nMigen. nMigen is a direct descendant of [Migen][] rewritten from scratch to address many issues that became clear in the many years Migen has been used in production. nMigen provides an extensive compatibility layer that makes it possible to build and simulate most Migen designs unmodified, as well as integrate modules written for Migen and nMigen.
nMigen is designed for Python 3.6 and newer. nMigen's Verilog backend depends on [Yosys][]; currently, the `master` branch of Yosys is required. nMigen is designed for Python 3.6 and newer. nMigen's Verilog backend requires [Yosys][] 0.9 or a newer version.
Thanks [LambdaConcept][] for being a sponsor of this project! Contact sb [at] m-labs.hk if you also wish to support this work. Thanks [LambdaConcept][] for being a sponsor of this project! Contact sb [at] m-labs.hk if you also wish to support this work.
@ -28,6 +28,8 @@ nMigen is *not* a "Python-to-FPGA" conventional high level synthesis (HLS) tool.
### Installation ### Installation
nMigen requires [Yosys][] 0.9 or newer, as well as a device-specific toolchain.
pip install git+https://github.com/m-labs/nmigen.git pip install git+https://github.com/m-labs/nmigen.git
pip install git+https://github.com/m-labs/nmigen-boards.git pip install git+https://github.com/m-labs/nmigen-boards.git