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back.rtlil: add assertions guarding against $\d+ port names.

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See #733.
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Catherine 2023-01-31 10:23:59 +00:00
parent 64b96e143b
commit 2ca421dea8
1 changed files with 7 additions and 0 deletions
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7
amaranth/back/rtlil.py
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@ -2,6 +2,7 @@ import io
from collections import OrderedDict from collections import OrderedDict
from contextlib import contextmanager from contextlib import contextmanager
import warnings import warnings
import re
from .._utils import bits_for, flatten from .._utils import bits_for, flatten
from ..hdl import ast, ir, mem, xfrm from ..hdl import ast, ir, mem, xfrm
@ -150,6 +151,9 @@ class _ModuleBuilder(_AttrBuilder, _BufferedBuilder, _Namer):
self._append(" wire width {} {}\n", width, name) self._append(" wire width {} {}\n", width, name)
else: else:
assert port_kind in ("input", "output", "inout") assert port_kind in ("input", "output", "inout")
# By convention, Yosys ports named $\d+ are positional, so there is no way to use
# a port with such a name. See amaranth-lang/amaranth#733.
assert port_id is not None
self._append(" wire width {} {} {} {}\n", width, port_kind, port_id, name) self._append(" wire width {} {} {} {}\n", width, port_kind, port_id, name)
return name return name
@ -177,6 +181,9 @@ class _ModuleBuilder(_AttrBuilder, _BufferedBuilder, _Namer):
self._append(" parameter \\{} {}\n", self._append(" parameter \\{} {}\n",
param, _const(value)) param, _const(value))
for port, wire in ports.items(): for port, wire in ports.items():
# By convention, Yosys ports named $\d+ are positional. Amaranth does not support
# connecting cell ports by position. See amaranth-lang/amaranth#733.
assert not re.match(r"^\$\d+$", port)
self._append(" connect {} {}\n", port, wire) self._append(" connect {} {}\n", port, wire)
self._append(" end\n") self._append(" end\n")
return name return name